- Y. Nakashima, M. Ikeda, and K. Asada,
"New method for calculating inductance on VLSI circuit,"
電子情報通信学会総合大会, pp.83, A-3-15, Mar. 2000,
- H. Yamaoka, M. Ikeda, and K. Asada,
"A High-Speed PLA with Latch Sense Amplifiers,"
電子情報通信学会総合大会, C-12-16, p. 111, Mar. 2000,
- K. Asada, M. Ikeda, and S. Komatsu,
"Approaches for Reducing Power Consumption in VLSI Bus Circuits,"
IEICE Trans. Electronics, Vol.E83-C, No.2, pp.153-160, Feb. 2000,
- T. Nezuka, T. Fujita, M. Ikeda, and K. Asada,
"A Binary Image Sensor with Flexible Motion Vector Detection using Block Matching Method,"
Proceedings of ASP-DAC 2000, University LSI Design Contest, A1.11, pp.21-22, Feb. 2000,
- T. Ishihara and K. Asada,
"A Memory Power Reduction Technique for Core-base System LSIs,"
電子情報通信学会 技術研究報告 VLD2000-85, VLD200-85, pp.95-100, 2000,
- M. Ikeda and K. Asada,
"A New Trial on HDL Exercise Class for Undergraduate School in EE Department,"
Proc. of 2000 European Workshop on Microelectronics Education(EWME 2000) in France, pp. 146--147, 2000,
- M. Ikeda, H. Aoki, and K. Asada,
"Voltage Bounce Testing in Power Supply Lines Using Onchip Voltage Scan Path,"
Technical Report of IEICE., CPM99-121, ICD99-127, pp. 9-14, Dec. 1999,
- T. Nezuka, M. Ikeda, and K. Asada,
"A Gray-Scale Image Sensor for Sub-pixel Level Motion Detection and Stereo Vision,"
Proceedings of 3rd Workshop on System VLSI in Biwako, pp.183-185, Nov. 1999,
- H. Ito and K. Asada,
"Extraction Method of Structural Parameters Using Backgate Characteristics of Subthreshold Slope Factor in Fully-Depleted SOI MOSFETs,"
電子情報通信学会論文誌 , Vol.J82-C-II, No.9, pp.498-504 , Sep. 1999,
- R. Hamada, S. Komatsu, M. Ikeda, and K. Asada,
"Statistical Analysis of Data Sequences on Microprocessor Data Bus Lines and Proposal of Models for Artificial Data Sequences,"
IEICE Trans. On Fundamentals of Electronics, Communications and Computer Sciences, Vol.J82-A, No.8, pp.1406-1408, Aug. 1999,
- K. Asada,
"Associative momory with minimum hammingdistance detector and its application to bus data encoding,"
Proc. of AP-ASIC 99, 16.1, Aug. 1999,
- M. Ikeda and K. Asada,
"Standard Design Flows of Logic LSIs in Japanese Universities and VDEC,"
Proc. of 1999 Micro Electronic Systems Education Conference (MSE 99), pp. 8-9, Jul. 1999,
- M. Ikeda and K. Asada,
"Standard Cell Library Generation and Standard Design Flow Establishment Through VDEC Chip Fabrication Pilot Project,"
Proceding of '99 DA Symposium, pp. 149-152, Jul. 1999,
- K. Seto, M. Ikeda, and K. Asada,
"Logic Resynthesis using SPFDs for Standard Cell ICs,"
DA Symposium '99, , Jul. 1999,
- M. Ikeda and K. Asada,
"Standard Cell Library Generation and Standard Design Flow Establishment Through VDEC Chip Fabrication Pilot Project,"
Proceding of '99 DA Symposium, pp. 149-152, Jul. 1999,
- K. Asada,
"VDEC:An Approach in Universities,"
電子情報通信学会誌, Vol.82,No.5, pp。454-457, May. 1999,
- T. Mido, H. Ito, and K. Asada,
"TEST Structure for Characterizing Capacitance Matrix of Multi-layer Interconnections in VLSI,"
IEICE Transactions on Electronics, Vol.E82-C, No.4, pp.570-575, Apr. 1999,
- S. Komatsu, M. Ikeda, and K. Asada,
"Adaptive Codeｂook Encoding for Low Power Chip Interface,"
電子情報通信学会論文誌 , Vol.J82-C-II, No.4, pp.203-209 , Apr. 1999,
- T. Mido, H. Ito, and K. Asada,
"TEST Structure for Characterizing Capacitance Matrix of Multi-layer Interconnections in VLSI,"
IEICE Trans.,Electronics, Special Issue on International Conference on Microelectronic Test Structures, Apr. 1999,
- S. Komatsu, K. Asada, and M. Ikeda,
"Adaptive Codebook Encoding for Low Power Chip Interface,"
電子情報通信学会論文誌C-II, Vol.J82-C-II, No.4, pp.203-209, Apr. 1999,