- 佐藤 純一 and 浅田 邦博,
(in Japanese) "パルテノンによるＲＩＳＣプロセッサの設計ーケーススタディー,"
パルテノン研究会, Oct. 1993,
- R. Ikeno and K. Asada,
"High-Speed Method for Device Simulations by Area Division,"
The Japan Society of Applied Physics, Sep. 1993,
- M. Lee and K. Asada,
"A Newly proposed for Delay Improvement on CMOS/SOI Future Technology,"
SISDEP 93, Vol.5, pp.349-352, Sep. 1993,
- 秋田 純一 and 浅田 邦博,
"A Method of Reducing Power Consumption of CMOS Logic Based on Signal Transition Probability,"
電子情報通信学会 VLSI設計技術研究会, ED-93-83, Sep. 1993,
- 池野 理門 and 浅田 邦博,
"High-Speed Method for Device Simulations by Area Division,"
第59回応用物理学会学術講演会, 28pーz7ー3、pp720, Sep. 1993,
- 張 洪明 and 浅田 邦博,
"A Layout Method for Logic System Designed by Parthenon,"
1993年電子情報通信学会 秋季全国大会, A-68, pp.1-68, Sep. 1993,
- 岩崎 靖和 and 浅田 邦博,
"Numerical Analysis of Power Devices with Axially Symmetric Structure,"
第54回応用物理学会 学術講演会, 28p-ZT-8, pp.722, Sep. 1993,
- 池田 誠 and 浅田 邦博,
"A Design of Control Circuits for Reduced Swing Signal Data Transmission Method,"
1993年電子情報通信学会 秋季全国大会, C-441, pp.5-151, Sep. 1993,
- M. Lee and K. Asada,
"A High Performance on CMOS/SOI Integrated Circuits with SIMOX Substrates,"
36th Midwest Symp. on Circuits and Systems (MWSCAS), Aug. 1993,
- M. Lee, M. Fujisahima, and K. Asada,
"A High Speed and Low Power on CMOS/SOI Technology,"
51st Device Research Conference (DRC), Session ⅡA, No.8, Jun. 1993,
- 池田 誠 and 浅田 邦博,
"High Speed Data Transmission Method by Reduced Swing Signal for VLSI Bus Architecture,"
電子情報通信学会 技術研究報告, ED93-5D, ICD93-49 pp.39-45, Jun. 1993,
- 藤島 実 and 浅田 邦博,
(in Japanese) "短チャネル低電源電圧CMOS回路における負荷容量の電気的評価法,"
電子情報通信学会技術研究報告, Vol.93, No.111, pp.1-7, Jun. 1993,
- M. Fujishima, K. Asada, Y. Omura, and K. Izumi,
"Low-power 1/2 Frequency Dividers Using 0.1μm CMOS Circuits Built with Ultrathin SIMOX Substrates,"
IEEE Journal of Solid-State Circuits, Vol.28, No.4, pp.510-512, Apr. 1993,
- 張 洪明 and 浅田 邦博,
"An optimal layout method based on compatible pair search algorithm ,"
第6回回路とシステム 軽井沢ワークショップ, pp.61-65, Apr. 1993,
- M. Lee, M. Fujishima, and K. Asada,
"Influence of Intrinsic and Extrinsic Capacitance on CMOS/SIMOX Inverter Delay,"
Proceedings of the 1993 IEICE Spring Conference, C-9, pp.5-203, Mar. 1993,
- M. Fujishima and K. Asada,
"Proposal of Standard Characterization Method for Dynamic Circuit Performance,"
Proc. IEEE Int. Conf. on Microelectronic Test Structure , Vol.6, pp.227-232, Mar. 1993,
- M. Lee, M. Fujishima, and K. Asada,
"Influence of Intrinsic and Extrinsic Capacitance on CMOS/SIMOX Inverter Delay,"
1993年電子情報通信学会 春季全国大会（IEICE）, C-573, Vol.5, pp.203, Mar. 1993,
- 張 洪明 and 浅田 邦博,
"A Transistor pairing method for complex gate CMOS networks,"
１９９３年電子情報通信学会 春季全国大会, A-95, pp.1-95, Mar. 1993,
- 池田 誠 and 浅田 邦博,
"Reduced Voltage Bus Lines using Termination Resistors,"
1993年電子情報通信学会 春季全国大会, C-572, pp.5-202, Mar. 1993,
- H. Zhang and K. Asada,
"A General and Efficient Mask Pattern Generator For Non-Series-parallel CMOS Transistor Network in "Synthesis for control dominated circuits","
Edited by G. Saucier, Elsevier Science Publishers BV., 1993,