- M. Ikeda
"Studies on Wide Dynamic Range Image Sensors,"
IST2008-42, pp. 21-24, Information Sensing Research Committee, The Institute of Image Information and Television Engineers(ITE), Sept.2008.
- J. Kim, K. Ikai, M. Ikeda, and K. Asada,
" Digital Transceiver Circuit Design for Immune Device Parameter Variation,"
IEICE Society Conference, Sep. 2008 , (in Japanese).
- K. Ikai, J. Kim, M. Ikeda, and K. Asada,
" Digital Integrated Circuit Design for Stripe-Shaped TFT,"
IEICE Society Conference, Sep. 2008 , (in Japanese).
- Y.K.Kim, M. Ikeda and K. Asada,
" Analysis of light transmission on multilayer interconnect for color CMOS image sensors,"
IEICE Society Conference, Sep. 2008 , (in Japanese).
- Y. Yachide, M. Ikeda, and K. Asada,
"FPGA-Based 3-D Engine for High-speed 3-D Measurement Based on Light-Section Method,"
Proc. of IEEE International Conference on Field-Programmable Technology (ICFPT), pp. 293 - 296,Dec. 2007,
- M. Ikeda, K. Ishii, T. Sogabe, and K. Asada,
"Datapath Delay Distributions for Data/Instruction Against PVT Variations in 90nm CMOS,"
Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), A4L-E04, pp. 154 - 157,Dec. 2007,
- M. Sasaki, M. Ikeda, and K. Asada,
"3.5-Gb/S Extended Frequency Range Wave-Pipeline PRBS Generator in 0.18-um CMOS,"
Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), B2L-C04, pp. 526 - 529,Dec. 2007,
- K. Kurihara, T. Iizuka, M. Ikeda, and K. Asada,
"Process Variation Aware Comprehensive Layout Synthesis for Yield Enhancement in Nano-Meter CMOS,"
in Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), C4L-F04, pp. 1296 - 1299,Dec. 2007,
- Y. Yachide, M. Ikeda, and K. Asada,
"Triangulation-based calibration method based on light-section method using spheres,"
Proc. of International Conference on Sensing Technology (ICST), pp. 399-403,Nov. 2007,
- M. Sasaki, M. Ikeda, and K. Asada,
"40 Frames/sec 16x16 Temperature Probe Array using 90nm 1V CMOS for On line Thermal Monitoring on VLSI Chip,"
in Proc. of IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 264-267,Nov. 2007,
- T. Nakura, T. Kazama, M. Ikeda and K. Asada,
"Study on Active Substrate Noise Cancelling Technique using Power Line di/dt Detector,"
CPM2007-128, ICD2007-139, pp.11-16Nov. 2007, (in Japanese).
- Y. Yachide, M. Ikeda, and K. Asada,
"Real-time and high-speed 3-D measurement based on FPGA-based 3-D calculation,"
Proc. of IEICE Society Conference 2007, A-3-6, p. 50,Sep. 2007, (in Japanese).
- Hai Dinh Minh Pham, T. Iizuka, M. Ikeda, and K. Asada,
"Shot Count Reduction Methodology for Character Projection Electron Beam Direct Writing (CP-EBDW),"
Proc. of IEICE Society Conference 2007, A-3-12, p. 56,Sep. 2007, (in Japanese).
- K. Ikai, M. Ikeda, and K. Asada,
"Digital Integrated Circuit Design for Stripe-Shaped TFT,"
Proc. of IEICE Society Conference 2007, A-3-13, p. 57,Sep. 2007, (in Japanese).
- K. Kurihara, T. Iizuka, M. Ikeda, and K. Asada,
"Evaluation of Cell Layout Considering Lithography Variation Tolerance,"
Proc. of IEICE Society Conference 2007, A-3-15, p. 59,Sep. 2007, (in Japanese).
- YunKyung Kim, M. Ikeda, and K. Asada,
"Analysis of light's attenuation on multi-dielectric layers of a CMOS image sensor,"
Proc. of IEICE Society Conference 2007, A-3-17, p. 61,Sep. 2007, (in Japanese).
- Caner Basci, M. Ikeda, and K. Asada,
"A Current-Mode Pixel-level Ambient Light Suppression Scheme for CMOS Smart Image Sensors,"
Proc. of IEICE Society Conference 2007, C-12-7, p. 62,Sep. 2007, (in Japanese).
- T. Iizuka, M. Ikeda, and K. Asada,
"Timing-Aware Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization,"
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, , Vol. 15, no. 6 , pp. 716--720, Jun. 2007,
- M. Ikeda
"Power Control for Self-Synchronous System --Instruction and Data Grain Power Control for Self-Synchronous System with Dynamic Voltage Scaling--,"
IEEE 2007 VAIL Computer Elements Workshop, Jun.2007.
- T. Iizuka, M. Ikeda, and K. Asada,
"OPC-Friendly De-Compaction with Timing Constraints for Standard Cell Layouts,"
in Proc. of IEEE International Symposium on Quality Electronic Design (ISQED),, pp. 776 -- 781,Mar. 2007,