- T. Ishihara and K. Asada,
"An Architectural Level Energy Reduction Technique for Deep-Submicron Cache Memories,"
ASP-DAC 2002 (India), pp.274-287, Jan. 2002,
- Y. Oike, M. Ikeda, and K. Asada,
"High-sensitivity and Wide-dynamic-range Position Sensor Using Logarithmic-response and Correlation Circuit,"
IEEE Int. Conf. on VLSI Design & ASP-DAC (the Best Design Award)", Jan. 2002,
- H. Yoshida, H. Yamaoka, M. Ikeda, and K. Asada,
"Logic Synthesis for PLA with 2-input Logic Elements,"
in Proc. of IEEE Int. Symp. on Circuits and System, pp.373-376, May 2002,
- T. Ishihara, S. Komatsu,M. Miyama,M. Yoshimoto, M. Hirata, M. Fujita and K. Asada,
"An Inter-University Joint Program for a Trial of IP-Based System LSI Design,"
Proc. of the 4th European Workshop on Microelectronics Education, pp.129-132, May 2002,,
- T. Ishihara and K. Asada,
"A System Level Optimization Technique for Application Specific Low Power Memories ,"
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E84-A, No.11, pp.2755-2761, Nov. 2001,
- K. Asada,
"Current status of VDEC IP project and future plan,"
電子情報通信学会技術研究報告 VLSI設計技術, VLSI2001-85-88, pp.1-13, Nov. 2001,
- H. Yoshida, H. Yamaoka, M. Ikeda, and K. Asada,
"Logic Synthesis for PLA with 2-input Logic Elements,"
電子情報通信学会技術報告, CPSY2001-72, Nov. 2001,
- T. Ishihara and K. Asada,
"A Leak Energy Reduction Techineque for Deep Submicron Cache Memories,"
信学技報 IEICE Technical Report, CPSY2001-61，pp.1-6, Nov. 2001,
- Y. Oike, M. Ikeda, and K. Asada,
"Design and Evaluation of High-sensitivity and Wide-dynamic-range Position Sensor for 3-D Measurement,"
第5回 システムLSIワークショップ, pp.307-310, Nov. 2001,
- T. Nezuka, M. Ikeda, and K. Asada,
"A High-Speed Position Sensor for 3-D Measurement with Column Parallel Readout,"
第5回システムLSIワークショップ, pp.231-234, Nov. 2001,
- S. Sugiyama, M. Ikeda, and K. Asada,
"Power Supply Noise Estimation Using Transfer Function,"
IEICE Technical Report, VLD2001-157, Nov. 2001,
- H. Yoshida, H. Yamaoka, M. Ikeda, and K. Asada,
"Logic Synthesis for PLA with 2-input Logic Elements,"
電子情報通信学会技術研究報告、北九州国際会議場, CPSY2001-72，pp.67-72, Nov. 2001,
- H. Yamaoka, M. Ikeda, and K. Asada,
"A High-Speed PLA using Dynamic Array Logic Circuits with Latch Sense,"
IEICE Transactions on Electronics, Vol.E84-C, No.9, pp.1240-1246, Sep. 2001,
- K. Asada, T. Nezuka, and Y. Oike,
"Smart Access Sensor,"
オプトロニクス, 9月号, pp.136-141, Sep. 2001,
- Y. Oike, M. Ikeda, and K. Asada,
"High-speed and High-accuracy Position Sensor for 3-D Measurement Using Row Parallel Processing on the Sensor Plane,"
電子情報通信学会技術研究報告, ICD2001-103, pp.83-88, Sep. 2001,
- Y. Oike, M. Ikeda, and K. Asada,
"Wide Dynamic Range Photo Detector for Smart Position Sensor Using Log-response and Correlation Circuit,"
Ext. Abst. of Int. Conf. of Solid State Devices and Materials, pp.282-283, Sep. 2001,
- T. Nezuka, M. Ikeda, and K. Asada,
"An Implementation Method of High-Speed Row Parallel Position Detection on Sensor Plane,"
電子情報通信学会技術研究報告, ICD2001-101, pp.67-74, Sep. 2001,
- J. Qiao and K. Asada,
"Functional Decomposition with Application to LUT-Based FPGA Synthesis,"
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E84-A No.8 p.2004-2013, Aug. 2001,
- H. Yamaoka and K. Asada,
"A Threshold Logic-Based High-Speed Hamming Distance Detector and Its Evaluation,"
電子情報通信学会技術研究報告 ICD, SDM2001-134, pp. 37-42, Aug. 2001,
- H. Yoshida, H. Yamaoka, M. Ikeda, and K. Asada,
"Logic Synthesis for XOR-Based Dual-Rail PLA,"
DAシンポジウム 情報処理学会 in Proc. of IPSJ DA Synposium, pp.31-36, Jul. 2001,