H. Yamaoka, M. Ikeda, and K. Asada,
"A High-Speed PLA with Latch Sense Amplifiers,"
Proc. of 4th Workshop on System VLSI in Biwako, pp.223-226, Nov. 2000,
T. Nezuka, M. Ikeda, and K. Asada,
"A Smart Image Sensor for Position Detection with a Quad-tree Scan Controller,"
Proceedings of 4th Workshop on System VLSI in Biwako, pp.183-185, Nov. 2000,
S. Komatsu, M. Ikeda, and K. Asada,
"Data Compression Encoding Method for High Throughput Data Transmission in VLSI,"
Proc. of 4th Workshop on System VLSI in Biwako, pp.215-218, Nov. 2000,
T. Nezuka, J. Akita, M. Ikeda, and K. Asada,
"A Smart Image Sensor with Novel Implementation of Quad-tree Scan,"
Proceedings of the 2nd IEEE Asia-Pacific Conference on ASIC, pp.135-138, Oct. 2000,
Y. Nakashima, M. Ikeda, and K. Asada,
"New method for calculating inductance on VLSI circuit and estimation of circuits by this method,"
信学技法, VLD2000-50, SDM2000-123, pp.17-22, Sep. 2000,
H. Yamaoka, Y. Nakashima, T. Nezuka, and 小松 聡,
"Designs in Asada-Ikeda Lab.,"
VDEC LSI デザイナーズフォーラム 2000/ VDEC LSI Designers Forum 2000,Sep. 2000,
T. Nezuka, M. Hoshino, M. Ikeda, and K. Asada,
"A Position Detection Sensor for 3-D Measurement,"
Proceedings of the 26th European Solid-State Circuits Conference, pp.412-415, Sep. 2000,
J. Qiao, M.Ikeda, and K.Asada,
"Optimum Functional Decomposition for LUT-based FPGA Synthesis,"
The 10th International Conference on Field-Programmable Logic and Applications, in Austria , pp.555-564, Aug. 2000,
M. Hoshino, T. Nezuka, M. Ikeda, and K. Asada,
"A 3-D Measurement System with a Smart Position Sensor,"
DAシンポジウム Proceedings of DA Symposium, pp.133-138, Jul. 2000,
K. Hoh and K. Asada,
(in Japanese) "大規模集積システム設計教育研究センター(VDEC)による集積回路の設計教育と試作の支援,"
平成12年度工学教育連合講演会「21世紀における日本の工学教育ー"ものづくり"と"創造性"」, 2000/05/10, May. 2000,
K. Seto, H. Yoshida, M. Ikeda, and K. Asada,
"Multi-Level Logic Optimization Using Node Complementation,"
IEEE/ACM International Workshop on Logic Synthesis, U.S.A., pp.291-294, May. 2000,
T. Nezuka, M. Hoshino, M. Ikeda, and K. Asada,
"A Gray-Scale Image Sensor for Motion Detection and 3-D Measurement,"
ロボティクスメカトロニクス講演会 Proceedings of JSME Conference on Robotics and Mechatronics, 1A1-50-069, May. 2000,
J. Qiao, M. Ikeda, and K. Asada,
"Optimum Functional Decomposition for LUT-based FPGA Synthesis,"
第13回 回路とシステム(軽井沢)ワークショップ (2000 IEICE, The 13th Workshop on Circuits and Systems) 2000 IEICE,, pp。119-124, Apr. 2000,
Y. Nakashima, M. Ikeda, and K. Asada,
"Computational Cost Reduction in Extracting VLSI Interconnect,"
2000年電子情報通信学会総合大会, A-3-15, Mar. 2000,
S. Komatsu, M. Ikeda, and K. Asada,
"Circuit Evaluation of Adaptive Code-Book Encoding for Low Power Chip-Interface,"
2000年電子情報通信学会総合大会, C-12-14, Mar. 2000,
T. Yamashita and K. Asada,
"CSPL: A Capacitor-Separated Pass-transistor Logic using Self Offset-Cancelling Sense Amplifier for high speed operation,"
2000年電子情報通信学会総合大会, C-12-17, Mar. 2000,
M. Hoshino and K. Asada,
"A 3-D Measurement System using Smart Image Sensor with Flexible Block Access,"
2000年電子情報通信学会総合大会, C-12-51, Mar. 2000,
H. Aoki, M. Ikeda, and K. Asada,
"On-Chip Voltage Noise Monitor for Measuring Voltage Bounce in Power Supply Lines Using a Digital Tester,"
International Conference on Microelectronic Test Structures 2000 (ICMTS2000) , Session4.9, Mar. 2000,
M. Ikeda, H. Aoki, and K. Asada,
"DVDT: Design for Voltage Drop Test using Onchip-Voltage Scan Path,"
2000 IEEE International Symposium on Quality Electronic Design(ISQED2000),, Mar. 2000 (To be presented), Mar. 2000,
M. Ikeda, H. Aoki, and K. Asada,
"Noise Measurement on Power Supply Lines using OnChip Voltage Scan Path,"
14th JIEP General Conference (第14回 エレクトロニクス実装学会 学術講演大会), Mar. 2000,