- T. Yamashita and K. Asada,
"High Speed Pass-transistor Logic with Capacitor separated sense amplifire,"
第2回システムLSI琵琶湖ワークショップ For the Interdisciplinary Materials Research, pp.233-235, Nov. 1998,
- M. Song and K. Asada,
"Design of Low Power Digital VLSI Circuits Based on a Novel Pass-transistor Logic,"
IEICE Trans. Electronics, Vol.E81-C, No.11, pp.1740-1749, Nov. 1998,
- T. Nezuka and K. Asada,
"An Image Sensor for Motion Compensation with Hierarchical Scan,,"
Technical Report of IEICE., DSP98-95, pp.43-48, Oct., 1998., Vol.98,No.318,DSP98-95,p.43-48, Oct. 1998,
- T. Mido and K. Asada,
"An Evaluation of Skin Effect on Hi-Frequency VLSI Interconnections using Numerical Simulation,"
第45回応用物理学会関係連合講演会. , 28p-L-8, p.11, Oct. 1998,
- T. Mido and K. Asada,
"An Analysis on Hi-Frequency Interconnections in VLSI Considering Skin Effect,"
通信学会VLSI設計研究会、信学技報, VLD98-84、Vol.98、No.2 pp.89-94, Oct. 1998,
- H. Ito and K. Asada,
"Device parameter extraction using subthreshold slope factor characteristics in SOI MOSFETs,"
第59回応用物理学会学術講演会, 15a-P9/II p.778, Oct. 1998,
- S. Komatsu, M. Ikeda, and K. Asada,
"Adaptive Code-Book Encoding for Low Power Chip-Interface,"
1998年電子情報通信学会ソサイエティ大会, C12-23, pp.114, Oct. 1998,
- K. Asada, T. Nezuka, and M. Ikeda,
"A High Speed CMOS Image Sensor with Hierarchical Access Path,"
1998年電子情報通信学会ソサイエティ大会, SC-10-5,pp184-185, Sep. 1998,
- K. Asada, T. Nezuka, and M. Ikeda,
"A High Speed CMOS Image Sensor with Hierarchical Access Path,"
1998年電子情報通信学会ソサイエティ大会講演論文集Proceedings of the 1998 Electronics Society Conference of IEICE, Pergamon, SC-10-5, p.184-185,, Sep. 1998,
- T. S. Cheung and K. Asada,
"Regenerative Pass-Transistor Logic: A Modular Circuit Technique for High Speed Logic Circuit Design,"
IEICE Trans. on Electronics , Vol.E-79C, No.9, pp.1274-1284, Sep. 1998,
- R. Zheng and K. Asada,
"Design of Completion Prediction Adder with Shift Operation and Its Aoolication to Microcessor ,"
通信学会、信学技報, VLD98-51, pp.51-56, Sep. 1998,
- R. Zheng and K. Asada,
"Design of a Completion Adder,"
通信学会全国大会講演論文集, C-12-22, pp.113, Sep. 1998,
- T. Mido, H. Ito, and K. Asada,
"TEST Structure for Direct Extraction of Capacitance Matrix in VLSI,"
1998 IEICE Fall Conference, C-12-1, pp.92, Sep. 1998,
- H. Ito and K. Asada,
"TEST Structure for Direct Extraction of Capacitance Matrix in VLSI,"
1998年電子情報通信学会ソサイエティ大会, C-12-1, pp.92, Sep. 1998,
- M. Ikeda and K. Asada,
"Time-Domain Minimum-Distance Detector and Its Application to Low Power Coding Scheme on Chip Interface,"
24th European Solid State Circuit Conference, pp.464-467, Sep. 1998,
- S. Komatsu, M. Ikeda, and K. Asada,
"Adaptive Code-Book Encoding for Low Power Chip-Interface,"
通信学会、信学技報, ICD98-176, pp.1-6, Sep. 1998,
- M．Aoyagi and K．Asada,
"Analysis of aluminum interconnection life time due to stress-induced migration on semiconductor device,"
Ext．Abstr． (59th Fall Meet．1998)； Japan Society of Applied Physics and Related Societies, 16p-ZL5．(in Japanese), Sep. 1998,
- K. Sekine, S. Nakai, T. Nishimura, K. Shimoi, K. Nishimura, and K. Asada,
"Progress in Electronics, Information and System Engineering,"
Journal of IEE of Japan, Vol.118, No.6, pp.348-354, Jun. 1998,
- K. Asada,
"Microelectronics education in Japan,"
Microelectronics Education 1998, Proceedings pp. 195-198, May. 1998,
- K. Asada,
"VDEC (VLSI Design and Education Center): The Center of VLSI Desigh Education in Japan,"
MRS-J NEWS , Vol.10, No.2, pp.4-5, May. 1998,