- 池野 理門, 伊藤 浩, and 浅田 邦博,
"Device Parameter Estimation by 1-D SOI Simulation Considering 2-D Quantum Effects,"
第56回応用物理学会学術講演会, 27a-ZQ-3, Aug. 1995,
- K. Asada and J. Akita,
"A Method for Reducing Power Consumption of CMOS Logic Based on Signal Transition Probability,"
IEICE Trans. on Electronics, Vol.E78-C, No.4, pp.436-440, Apr. 1995,
- 池野 理門, 名倉 徹, and 浅田 邦博,
"Estimation of SOI MOSFET Threshold Voltage Using 1-D Device Simulation Method,"
第42回応用物理学関係連合講演会, Mar. 1995,
- 池野 理門, 伊藤 浩, 名倉 徹, and 浅田 邦博,
"Evaluation of SOI MOSFET Threshold Voltage using 1-D Device Simulation,"
電子情報通信学会 シリコン材料・デバイス研究会, SDM94-208, Mar. 1995,
- 伊藤 浩 and 浅田 邦博,
"Leak Current Characterization in high Frequency Operation of CMOS/SOI Circuits,"
第42回応用物理学会関係連合講演会, Mar. 1995,
- 張 子誠 and 浅田 邦博,
"A Low Power Digital Design Technique,"
1995年電子情報通信学会 春季全国大会, Mar. 1995,
- J. Akita and K. Asada,
"An Estimation of State Code Assignment for Low Power Finite State Circuit,"
1995年電子情報通信学会 春季全国大会, A-108, pp.108, Mar. 1995,
- K. Asada, M. Ikeda, and J. Akita,
"VLSI Design with Verilog HDL,"
1995年電子情報通信学会 春季全国大会, GD-2-6, Mar. 1995,
- 池田 誠 and 浅田 邦博,
"Power Optimization Method for Partitioned Bus Architecture,"
1995年電子情報通信学会 春季全国大会, Mar. 1995,
- 浅田 邦博 and 池田 誠,
"Design of General Purpose Microprocessor using Partitioned Bus Architecture,"
1995年電子情報通信学会 春季全国大会, Mar. 1995,
- 名倉 徹, 池野 理門, and 浅田 邦博,
"Analytical Model for Back Gate Effect on SOI Device,"
第42回応用物理学関係連合講演会, Mar. 1995,
- 池野 理門 and 浅田 邦博,
"Optimization of VLSI Process Parameters Using Circuit Simulation,"
1995年電子情報通信学会 春季全国大会, Mar. 1995,
- H. Ito and K. Asada,
"Leak Current Characterization in High Frequency Operation of CMOS Circuits Fabricated on SOI Substrate,"
IEEE Proc. International Conference on Microelectronics Test Structure, Mar. 1995,
- Minkyu Song and K. Asada,
"Design Methodology for Low Power Data Compressors Based on a Window Detector in a 54 x 54 Bit Multiplier,"
IEEE International Conference on Circuits and Systems (ISCAS'95) /IEEE Trans. Circuits Syst., pp.1568-1571, 1995,
- M. Ikeda and K. Asada,
"A Power Reduction Method using Partitioned Bus Architecture in High-Level VLSI Design ,"
IFIP Workshop on Logic and Architecture Synthesis, pp.225-230, Dec. 1994,
- K. Asada and J. Akita,
"Optimum State Assignment for CMOS Implementation of Low Power Finite State Machine,"
IFIP Workshop on Logic and Architecture Synthesis, pp.141-146, Dec. 1994,
- T. S. Cheung and K. Asada,
"A Single-Phase Clock Complementary Circuit Technique for Low Power Logic Circuit Design,"
Proc. ASICON 1994, Beijing, China, No.4.20, pp.275-278, Oct. 1994,
- H. Zhang, K. Asada, and T. S. Cheung,
"A Layout Design Method of High Speed CMOS VLSIs for Minimizing Power Consumption,"
Proc. ASICON 1994, Beijing, China, No.4.38, pp.348-351, Oct. 1994,
- T. S. Cheung, M. K. Song, and K. Asada,
"A Self-Refreshable Analog Memory Using Window Detector,"
Proc. ASICON 1994, Beijing, China, No.3.3, pp.145-148, Oct. 1994,
- 池田 誠 and 浅田 邦博,
"A Power Consumption Reduction Method using Partitioned and Reduced-Swing Bus Lines in High-Level Syntesis ,"
1994年電子情報通信学会 秋季全国大会, A-69, Sep. 1994,