- H. Yabe, M. Ikeda
"3-D Range Map Acquisition System Based on CMOS Image Sensor Using Time-Multiplexing Structured Pattern,"
IEICE Trans. on Electronics, Vol. E95-C, No.4, pp. 635-642,Apr. 2012.
- B. Devlin, M. Ikeda, and K. Asada,
"Gate-level Process Variation Offset Technique by using Dual Voltage Supplies to Achieve Near-threshold Energy Efficient Operation,"
IEEE Symposium on Low-Power and High-Speed Chips (COOL chips XV), Yokohama, Japan, Apr. 2012.
- T.-W. Chen and M. Ikeda,
"A Millimeter-Wave Resistor-less Pluse Generator with a New Diple-Patch Antenna in 65-nm CMOS,"
IEEE Symposium on Low-Power and High-Speed Chips (COOL chips XV), Yokohama, Japan, Apr. 2012.
- M. Abbas, T. J. Yamaguchi, Y. Furukawa, S. Komatsu, K. Asada,
"Low Delay Dispersion Comparator for Level-Crossing ADCs,"
2012 Japan-Egypt Conference on Electronics, Communications and ComputersMar. 2012.
- T. Nakura, K. Asada,
"Low Pass Filter-less Pulse Width Controlled PLL Using Time to Soft Thermometer Code Converter,"
IEICE Trans. on Electronics, Vol. E95-C, No.2, pp. 297-302,Mar. 2012.
- X. Fu, M. Ikeda
"Evaluation of Background Light Suppression Characteristic and Range Finding Accuracy for 3-D Measurement using Smart Imgae Sensor,"
ITE Technical Report, Vol. 36, No. 18, pp. 27-30,Mar. 2012.
- Takashi Maruyama, Yasuhide Machida, Shinji Sugatani, Hiroshi Takita,
Hiromi Hoshino, Toshio Hino, Masaru Ito, Akio Yamada, Tetsuya Iizuka,
Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada,
"CP Element Based Design for 14nm Node EBDW High Volume Manufacturing,"
in Proceedings of the SPIE Advanced Lithography (Alternative
Lithographic Technologies IV), Vol. 8323, Paper 8323-39,Feb. 2012.
- 池野理門，丸山隆司，飯塚哲也，小松聡，池田誠，浅田邦博,
"キャラクタプロジェクションによる電子ビーム直描技術におけるビア層のスループット向上とステンシル面積削減のための配線設計およびキャラクタ抽出"
DAシンポジウム2012論文集, 情報処理学会シンポジウムシリーズVol.2012, No.5, 5B-2, pp.187-192,Aug 2012.
- Rimon Ikeno, Takashi Maruyama, Tetsuya Iizuka, Satoshi Komatsu, Makoto
Ikeda, and Kunihiro Asada,
"Interconnect Design and Character Extraction Method for Throughput
Enhancement and Stencil Area Reduction of VIA Layer Exposure for
Electron Beam Direct Writing with Character Projection Technique,"
in Proceedings of IPSJ DA Symposium 2012,Aug 2012.
- K. Kodama, T. Iizuka, T. Nakura, K. Asada,
"Frequency Resolution Enhancement for Digitally-Controlled Oscillator
based on a Single-Period Switching Scheme"
The Workshop about LSI and Systems 2012, Kokura, Japan, May 2012.
- K.Kodama and M. Ikeda
"High-Voltage Capacitance Measurement Circuit for MEMS-Integrated LSI",
IEICE Technical Report, vol. 111, no. 497, pp. 7-12,Mar. 2012 .
- T. W. Chen and M. Ikeda
"Analysis of On-Line Clustering Algorithm for Low-Power Hardware Implementation,"
IEICE General Conference 2012, D-6-4,Mar. 2012 .
- T. Kikkawa, T. Nakura, K. Asada
"An Effect of Variability to RF Circuits for Phased Array Systems,"
IEICE General Conference 2012, C-12-71,Mar. 2012 , (in Japanese).
- H. Yabe and M. Ikeda
"A study on improving modulated light detection performance in the presence of background light,"
IEICE General Conference 2012, C-12-34,Mar. 2012 .
- N. N. Mai Khanh, M. Sasaki and K. Asada,
"A 65-nm CMOS Fully Integrated Shock-Wave Antenna Array with On-chip Jitter and Pulse-Delay Adjustment for Millimeter-Wave Active Imaging Application,"
IEICE Trans. on Electronics, Vol. E94-A, No.12, pp. 2554-2562,Dec. 2011.
- M. Abbas, T. J. Yamaguchi, Y. Furukawa, S. Komatsu, K. Asada,
"Novel technique for minimizing the comparator delay dispersion in 65nm CMOS technology,"
18th IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 220-223,Dec. 2011.
- B. Devlin, M. Ikeda, and K. Asada,
"Gate-Level Autonomous Watchdog Circuit for Error Robustness Based on a 65nm Self Synchronous System,"
in Proceedings of IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp. 53-57,Dec. 2011.
- S. Bushnaq, M. Ikeda, and K. Asada.,
"All-digital 400∼900 MHz power amplifier consuming 0.03 mW/MHz using 0.18 μm CMOS,"
in Proceedings of IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp. 607-610,Dec. 2011.
- T. Iizuka, M. Ikeda, and K. Asada,
"Timing-Aware Cell Layout Regularity Enhancement for Reduction of Systematic Gate Critical Dimension Variation,"
AICIT Journal of Next Generation Information Technology, Vol. 2, No. 4, pp. 1-9,Nov. 2011.(invited)
- N. N. Mai Khanh, M. Sasaki and K. Asada,
"A 0.25-um Si-Ge Fully Integrated Pulse Transmitter with On-chip Loop Antenna Array towards Beam- Formability for Millimeter-Wave Active Imaging,"
IEICE Trans. on Electronics, Vol. E94-C, No.10, pp. 1626-1633Oct. 2011.