- B. Devlin, M. Ikeda, and K. Asada
"A 65 nm Gate-Level Pipelined Self-Synchronous FPGA for High Performance and Variation Robust Operation ,"
IEEE Journal of Solid-State Circuits, Vol. 46, No.11, pp. 2500-2513,Oct. 2011.
- T. J. Yamaguchi, M. Soma, T. Aoki, Y. Furukawa, K. Degawa, K. Asada, M. Abbas, S. Komatsu,
"Application of a continuous-time level crossing quantization method for timing noise measurements,"
2011 IEEE International Test Conference (ITC),
Sep. 2011.
- J. Kim, T. Nakura, H. Takata, K. Ishibashi, M. Ikeda, and K. Asada
"On-Chip Resonant Supply Noise Reduction Utilizing Switched Parasitic Capacitors of Sleep Blocks with Tri-Mode Power Gating Structure"
in Proceedings of IEEE European Solid-State Circuit Conference (ESSCIRC), pp.183-186, Sep. 2011,
- K. Kodama, T. Iizuka, and K. Asada,
"A High Frequency Resolution Digitally Controlled Oscillator Using Single-Period Switching Scheme"
in Proceedings of IEEE European Solid-State Circuit Conference (ESSCIRC), pp.399-402, Sep. 2011,
- T. Kikkawa, T. Nakura, and K. Asada
"An Automatic Phase Control Circuit with DLL-like Architecture for Phased Array Antenna Systems"
Asia Symposium on Quality Electronic Design (ASQED), Kuala Lumpur, Malaysia, Sep. 2011.
- N. N. Mai Khanh, Masahiro SASAKI, and Kunihiro ASADA
"A Millimeter-wave Resistorless Pulse Generator with a New On-chip Dipole Patch Antenna in 65-nm CMOS,"
the 9th IEEE NEWCAS, France, The 3rd place of Best Student Paper Award, Sep. 2011.
- T. Kikkawa, T. Nakura, and K. Asada
"An Automatic Phase Control Circuit with DLL-like Architecture for Phased Array Antenna Systems"
Asia Symposium on Quality Electronic Design (ASQED), Kuala Lumpur, Malaysia, Best Paper Award Sep. 2011.
- B.S. Devlin, M. Ikeda, and K. Asada,
"Energy Minimum Operation in a Reconfigurable Gate-level Pipelined and Power-Gated Self Synchronous FPGA,"
in Proceedings of International Symposium on Low Power Electronics and Design (ISLPED), pp. 3-8,
Aug. 2011.
- T. Iizuka and K. Asada,
"All-Digital PMOS and NMOS Process Variability Monitor Utilizing Shared Buffer Ring and Ring Oscillator,"
IEICE Technical Report, vol. 111, no. 151, pp. 63-68,Jul. 2011.
- J. Kim, T. Nakura, H. Takata, K. Ishibashi, M. Ikeda, and K. Asada,
"On-Chip Resonant Supply Noise Reduction Using Active Decoupling Capacitors,"
IEICE Technical Report, vol. 111, no. 151, pp. 69-72,Jul. 2011.
- S. Mandai, T. Iizuka, T. Nakura, M. Ikeda, and K. Asada,
"1.0ps Resolution Time-to-Digital Converter based on Cascaded Time-Difference-Amplifier utilizing Differential Logic Delay Cells,"
IEICE Trans. on Electronics, Vol. E94-C, No.6, pp. 1098-1104,Jun. 2011.
- N.N.M. Khanh, M. Sasaki, and K. Asada
"A Millimeter-Wave Resistor-less Pluse Generator with a New Diple-Patch Antenna in 65-nm CMOS,"
IEEE International NEWCAS conference, Jun. 2011.
- H. Yabe, and M. Ikeda
"CMOS Image Sensor for 3-D range map acquisition Using Time Encoded 2-D Structured Pattern,"
International Image Sensor Workshop, Hokkaido, Japan, Jun. 2011,
- T. J. Yamaguchi, M. Abbas, M. Soma, T. Aoki, Y. Furukawa, K. Degawa, S. Komatsu, and K. Asada,
"An Equivalent-Time and Clocked Approach for Continuous-T ime Quantization,"
IEEE International Symposium on Circuits and Systems 2011 (ISCAS 2011), pp. 2529-2532,
May. 2011.
- S. Mandai, T. Nakura, T. Iizuka, M. Ikeda, and K. Asada,
"Cascaded Time Difference Amplifier With Differential Logic Delay Cell,"
IEICE Trans. on Electronics, Vol. E94-C, No.4, pp. 654-662,Apr. 2011.
- J. Kim, T. Nakura, H. Takata, K. Ishibashi, M. Ikeda, and K. Asada,
"On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch,"
IEICE Trans. on Electronics, Vol. E94-C, No.4, pp. 511-519,Apr. 2011.
- T. Iizuka, J. Jeong, T. Nakura, M. Ikeda, and K. Asada,
"All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter,"
IEICE Trans. on Electronics, Vol. E94-C, No.4, pp. 487-494,Apr. 2011.
- J. Kim, T. Nakura, H. Takata, K. Ishibashi, M. Ikeda, and K. Asada,
"Decoupling Capacitance Boosting for On-Chip Resonant Supply Noise Reduction,"
in Proceedings of IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pp. 111-114,
Apr. 2011.
- T. Iizuka and K. Asada,
"An All-Digital On-Chip PMOS and NMOS Process Variability Monitor Utilizing Shared Buffer Ring and Ring Oscillator,"
in Proceedings of IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pp. 115-120,
Apr. 2011.
- M. Ikeda,
"PVT and Aging Torelant Systems Employing Self-Synchronous Operation,"
Symposium LAAS/University of Tokyo GCOE Program : Secure Life Electronics, Mar. 2011.