- S. Mandai, T. Momma, M. Ikeda, and K. Asada,
"Variable Length Coded Address Compression for High-Speed 3-D Range-Finder Using Light-Section Method,"
IEICE Trans. On Electronics, Vol. E94-C, No.1, pp. 124-127,Jan. 2011.
- S. Ergun, U. Guler, and K. Asada,
"A High Speed IC Truly Random Number Generator Based on Chaotic Sampling of Regular Waveform,"
IEICE Trans. On Electronics, Vol. E94-A No.1 pp.180-190,Jan. 2011.
- T. Iizuka and K. Asada,
"All-Digital Ramp Waveform Generator for Two-Step Single-Slope ADC,"
IEICE Electronics Express, vol. 8, no.1, pp. 20-25 Jan. 2011.
- N.N.M. Khanh, M. Sasaki and K. Asada,
"A Fully Integrated Shock Wave Trasmitter with an On-chip Dipole Antenna for Pulse Beam-Formability in 0.18-μm CMOS,"
University Design Contest, 16th Asian and South Pacific Design Automation Conf. (ASP-DAC), Yokohama, Japan, pp. 107-108,Jan. 2011.
- J. Jeong, T. Iizuka, T. Nakura, M. Ikeda and K. Asada,
"All-Digital PMOS and NMOS Process Variability Monitor Utilizing Buffer Ring with Pulse Counter,"
in Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 79-80,Jan. 2011.
- B.S. Devlin, M. Ikeda, and K. Asada,
"A Gate-level Pipelined 2.97GHz Self Synchronous FPGA in 65nm CMOS,"
in Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 25-28, Jan. 2011.
- K. Asada,
"Solutions for Side Effect of Low Voltage Operation in Deep Sub‐micron VLSI Circuits,"
Plenary Talk in IEEE International SoC Design Conference 2011,Nov.2011.
- T. Nakasato, T. Nakura, and K. Asada,
"Stress-Balance Flip-Flops for NBTI Tolerant Circuit based on Fine-Grain Redundancy,"
in Proceedings of IEEE International SoC Design Conference (ISOCC), pp.150-153,Nov.2011.
- T. Kikkawa, T. Nakura, K. Asada
"An Automatic Phase Control Circuit for Phased Array Antenna Systems"
IEICE Society Conference, C-12-28, p. 103, Sep. 2011 , (in Japanese).
- H. Yabe, M. Ikeda
"3-D Range Map Acquisition System Based on CMOS Image Sensor"
Technical Group on Information Sensing Technologies, Sep. 2011 , (in Japanese).
- N.N.M. Khanh, M. Sasaki and K. Asada,
"Integrated Wideband Dipole Antenna for Pulse Beam-Fomability by Using 0.18μm CMOS Technology,"
Asia-Pacific Microwave Conference (APMC), Yokohama, Japan, pp. 1561-1564,Dec. 2010.
- T. Nakura
"Time difference amplifier, from getting idea to presenting at a conference,"
電子情報通信学会研究報告集積回路研究会, ICD2010-117, pp. 107-111,Dec.2010,
- M. Abbas, Y. Furukawa, S. Komatsu, T. J. Yamaguchi, and K. Asada,
"Clocked Comparator for High-Speed Applications in 65nm Technology,"
IEEE Asian Solid-State Circuits Conference 2010 (A-SSCC2010), pp. 277-280,Nov. 2010.
- J. Jeong, T. Iizuka, T. Nakura, M. ikeda and K. Asada,
"A Robust Pulse Delay Circuit Utilizing a Differential Buffer Ring,"
in Proceedings of International SoC Design Conference (ISOCC), pp. 272-275Nov. 2010.
- M. Ikeda,
"[Plenary Talk] Dependable System against PVT and Aging Employing Self-Synchronous Operation,"
ISOCC 2010, Nov. 2010.
- T. Iizuka, J. Jeong, T. Nakura, M. Ikeda, and K. Asada,
"Buffer-Ring-Based All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Measurement,"
IEEE/ACM Workshop on Variability Modeling and Characterization (VMC), San Jose, USA,Nov. 2010.
- M. Sasaki, N.N.M. Khanh, and Kunihiro Asada,
"A Circuit for on-Chip Skew Adjustment with Jitter and Setup Time Measurement,"
2010 IEEE Asian Solid-State Circuits Conference (ASSCC), Beijing, China, Nov. 2010.
- B.S. Devlin, M. Ikeda, and K. Asada,
"A 65nm 2.97GHz Self Synchronous FPGA with 42% Power Bounce Tolerance,"
in Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 8-10, Nov. 2010.
- M. Ikeda, and Y. Kim,
"Measurement and Analysis on Characteristics of Transmission and Polarization for 12ML 65nm CMOS,"
IEEE Sensors, pp. 548-551, Nov. 2010.
- T. Nakura,
"Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Block,"
in Proceedings of 10th Taiwan-Japan Microelectronics Symposium,Oct. 2010.