- T. Iizuka, M. Ikeda, and K. Asada,
"Yield-Optimized Standard Cell Layout IP Synthesis System,"
the 8th IP Award from LSI IP Design Award CommitteesMay. 2006,(IP Award).
- T. Iizuka, M. Ikeda, and K. Asada,
"Timing-Driven Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization,"
in Proc. of IEEE/ACM Design, Automation and Test in Europe (DATE), pp. 884 -- 889,Mar. 2006,
- M. Abbas, M. Ikeda, and K. Asada,
"On-Chip Detector for Single-Event Noise Sensing with Voltage Scaling Function,"
IEICE Trans. on Electron,Vol.E89-C, No.3, pp.370-376,Mar. 2006,
- T. Nakura, M. Ikeda, and K. Asada,
"Feedforward Active Substrate Noise Cancelling Based on di/dt of Power Supply,"
IEICE Trans. on Electron, Vol.E89-C, No.3, pp.364-369,Mar. 2006,
- H. Yamauchi, M. Ikeda, K. Asada,
"Degradation of Tamper Resistant LSI by Parameter Variation of Scaled Devices and its Countermeasures,"
IEICE Technical Report, IT2005-79, pp.87-92,Mar. 2006,
- T. Iizuka, M. Ikeda, and K. Asada,
"Exact Minimum-Width Multi-Row Transistor Placement for Dual and Non-Dual CMOS Cells,"
in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 5431 -- 5434,May 2006,
- T. Iizuka, M. Ikeda, and K. Asada,
"Exact Minimum-Width Transistor Placement for Dual and Non-Dual CMOS Cells,"
IEICE Trans. on Fundamentals,Vol. E88-A, No. 12, pp. 3485 -- 3491, Dec. 2005,
- T. Nakura, M. Ikeda, and K. Asada,
"On-chip di/dt Detector IP for Power Supply,"
in Proc. of IP Based SoC Design Conference & Exhibition (IP-SOC), pp.160 -- 164,Dec. 2005,
- H. Yoshida, M. Ikeda, and K. Asada,
"An Algebraic Approach for Transistor Circuit Synthesis,"
in Proc. of IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp. --,Dec. 2005,
- M. Abbas, M. Ikeda, and K. Asada,
"On-Chip Non-Periodic High-Swing Noise Detector,"
in Proc. of IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp. --,Dec. 2005,
- T. Iizuka, M. Ikeda, and K. Asada,
"Timing-Driven Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization,"
IEICE Technical Report, vol. 105, no. 442, pp. 79 - 84,Dec. 2005,
- H. Yoshida, M. Ikeda, and K. Asada,
"Exact Minimum Logic Factoring via Quantified Boolean Satisfiability,"
IEICE Technical Report, vol. 105, no. 443, pp. 41 - 46,Dec. 2005,
- T. Nakura, M. Ikeda, and K. Asada,
"On-chip di/dt Detector IP for Power Supply,"
IP Based SoC Design Conference & Exhibition (IP-SOC)Dec. 2005,(Best Paper Award).
- K. H. Dia, R. Zheng, M. Ikeda, and K. Asada,
"Footless Dual-Rail Domino Circuit with Self-Timed Precharge Scheme,"
in Proc. of IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 309 -- 312,Nov. 2005,
- M. Ikeda, Y. Yachide, Y. Oike, and K. Asada,
"Wavelength Identification Sensor Using MOS Photo-transistor Array Based on Metal Slit Diffraction,"
in Proc. of International Conference on Sensing Technology (ICST), pp. 683 -- 686,Nov. 2005,
- K. Yamamoto, M.Ikeda, and K. Asada,
"Stereo Vision with Random Pattern Light Projection,"
ITE Technical Report, vol. 29, no. 67, pp. 13 - 16,Nov. 2005,
- M. Abbas, M. Ikeda, and K. Asada,
"On-chip Detector for Non-Periodic High-Swing Noise Detection,"
in Proc. of International SoC Design Conference (ISOCC), pp. 231 -- 234,Oct. 2005,
- T.Kazama, M. Ikeda, and K. Asada,
"Shot Reduction Technique for Character Projection Lithography using combined cell stencil,"
in Proc. of SPIE BACUS Symposium on Photomask Technology, pp. 5992-5996,Oct. 2005,
- M. Abbas, M. Ikeda and K. Asada,
"On-chip Detector for Non-Periodic High-Swing Noise Sensing,"
in Proc. of International SOC Design Conference (ISOCC), pp.231-234,Oct. 2005,
- T. Nakura, M. Ikeda, and K. Asada,
"Autonomous di/dt Noise Control Scheme for Margin Aware Operation,"
IEEE European Solid-State Circuit Conference (ESSCIRC), sess.8.G.2, pp.467-470, Sep. 2005,