- K. Asada, T. Nezuka, and Y. Oike,
"Smart Access Sensor,"
オプトロニクス, 9月号, pp.136-141, Sep. 2001,
- J. Qiao and K. Asada,
"Functional Decomposition with Application to LUT-Based FPGA Synthesis,"
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E84-A No.8 p.2004-2013, Aug. 2001,
- T. Nezuka, T. Fujita, M. Ikeda, and K. Asada,
"A Binary Image Sensor for Motion Detection,"
Journal of Robotics and Mechatronics, Vol.12 No.5, pp.508-514, Jun. 2001,
- K. Hoh, K. Asada, and M. Ikeda,
(in Japanese) "大規模集積システム設計教育研究センターによるVLSI設計教育・研究の支援,"
電気学会論文誌C(電子・情報・システム部門誌) Trans. IEE of Japan, Vol.121-C, No.3, pp.488-491, Mar. 2001,
- T. Yamashita and K. Asada,
"Offset-Cancelling Sense Amplifier Applied with Pass-Transistor Logic ,"
電子情報通信学会論文誌 C , Vol.J84-C, No.2, pp.144-150, Feb. 2001,
- T. Nezuka, M. Hoshino, M. Ikeda, and K. Asada,
"A Smart Image Sensor with Quad-tree Scan,"
Journal of Image Information and Television Engineers, Vol.55, No.2, pp.287-292, Feb. 2001,
- T. Yamashita and K. Asada,
"CSPL: A Capacitor-Separated Pass-Transistor Logic for High Speed and Low Voltage Operation,"
電子情報通信学会論文誌 C , Vol.J83-C, No.6, pp.479-486, Jun. 2000,
- S. Komatsu, M. Ikeda, and K. Asada,
"Adaptive codebook encoding for low-power chip interface,"
IEICE Transactions on Electronics, Vol.E83-C, No.6, pp. 1001-1008, Jun. 2000,
- T. Mido, H. Ito, and K. Asada,
"A Simple and Efficient Measurement Method for Characterizing Capacitance Matrix of Multilayer Interconnection in VLSI,"
IEEE Transacions on Semiconductor Manufacturing, Vol.13, No.2, pp.145-151, May. 2000,
- K. Asada, M. Ikeda, and S. Komatsu,
"Approaches for Reducing Power Consumption in VLSI Bus Circuits,"
IEICE Trans. Electronics, Vol.E83-C, No.2, pp.153-160, Feb. 2000,
- H. Ito and K. Asada,
"Extraction Method of Structural Parameters Using Backgate Characteristics of Subthreshold Slope Factor in Fully-Depleted SOI MOSFETs,"
電子情報通信学会論文誌 , Vol.J82-C-II, No.9, pp.498-504 , Sep. 1999,
- R. Hamada, S. Komatsu, M. Ikeda, and K. Asada,
"Statistical Analysis of Data Sequences on Microprocessor Data Bus Lines and Proposal of Models for Artificial Data Sequences,"
IEICE Trans. On Fundamentals of Electronics, Communications and Computer Sciences, Vol.J82-A, No.8, pp.1406-1408, Aug. 1999,
- K. Asada,
"VDEC:An Approach in Universities,"
電子情報通信学会誌, Vol.82,No.5, pp。454-457, May. 1999,
- T. Mido, H. Ito, and K. Asada,
"TEST Structure for Characterizing Capacitance Matrix of Multi-layer Interconnections in VLSI,"
IEICE Transactions on Electronics, Vol.E82-C, No.4, pp.570-575, Apr. 1999,
- S. Komatsu, M. Ikeda, and K. Asada,
"Adaptive Codeｂook Encoding for Low Power Chip Interface,"
電子情報通信学会論文誌 , Vol.J82-C-II, No.4, pp.203-209 , Apr. 1999,
- T. Mido, H. Ito, and K. Asada,
"TEST Structure for Characterizing Capacitance Matrix of Multi-layer Interconnections in VLSI,"
IEICE Trans.,Electronics, Special Issue on International Conference on Microelectronic Test Structures, Apr. 1999,
- S. Komatsu, K. Asada, and M. Ikeda,
"Adaptive Codebook Encoding for Low Power Chip Interface,"
電子情報通信学会論文誌C-II, Vol.J82-C-II, No.4, pp.203-209, Apr. 1999,
- M. Aoyagi and K. Asada,
"Vacancy Distribution in Aluminum Interconnection on Semiconductor Device,"
Jpn.J.Appl.Physics, Part 1, No.4A, Vol.38(1999), p.1909-1914, Apr. 1999,
- T. Mido, H. Ito, and K. Asada,
"TEST Structure for Characterizing Capacitance Matrix of Multi-layer Interconnections in VLSI,"
IEICE Transactions on Electronics, Vol.E82-C, No.4, pp.570-575, Apr. 1999,
- M. Song and K. Asada,
"Design of Low Power Digital VLSI Circuits Based on a Novel Pass-transistor Logic,"
IEICE Trans. Electronics, Vol.E81-C, No.11, pp.1740-1749, Nov. 1998,