Ikeda Lab.

Journal

論文誌等での発表

  • Makoto Ikeda and K. Asada, "Data Bypassing Register File for Low Power Microprocessor," IEICE Transaction on Electronics, Vol.E78-C, No.10, pp.1470-1472, Oct. 1995,
  • Christoph Wasshuber and K. Asada, "Non-Approximate Evaluation of Macroscopic Quantum Tunneling of Charge for the Two-Junction Case at Arbitrary Temperatures and Bias Voltages," Jpn.J.Appl.Phys. , Vol.34(1995), PP.l1230-l1233, Part 2, No.9B, Sep. 1995,
  • K. Asada and J. Akita, "A Method for Reducing Power Consumption of CMOS Logic Based on Signal Transition Probability," IEICE Trans. on Electronics, Vol.E78-C, No.4, pp.436-440, Apr. 1995,
  • K. Asada and M. Lee, "Ultimate Lower Bound of Power for MOS Integrated Circuits and their Applications," IEICE Trans. on Electronics, Vol.E77-C, No.7, pp.1131-1137, Jul. 1994,
  • K-R. Cho, K. Okura, and K. Asada, "Experimental Design of a 32-bit Fully Asynchronous Microprocessor (FAM)," IEICE Trans. on Electronics, Vol.E77-C, No.4, Apr. 1994,
  • Y. Iwasaki and K. Asada, "Numerical Analysis of Durable Power MOSFET Using Cylindrical Device Simulator," IEICE Trans. Fundamentals, Vol.E77-A, No.2, pp.371-379, Feb. 1994,
  • M. Ikeda and K. Asada, "A proposal of high speed and low power data transmission method for VLSIs by reduced-swing signal," IEICE Transaction on Electronics, E76-A No.10 pp1666-1675, Oct. 1993,
  • M. Lee and K. Asada, "Deep-Submicron CMOS/SIMOX Delay Modeling by Time-Dependent Capacitance Model," IEEE Trans. on Electron Devices , Vol.40, No.10, pp.1897-1901, Oct. 1993,
  • M. Lee and K. Asada, "A New proposal for Delay Improvement on CMOS/SOI Future Technology," IEICE Trans. on Electronics, Vol.E76-C, No.10, pp.1513-1522, Oct. 1993,
  • M. Fujishima and K. Asada, "A Nonpinchoff Gradual Channel Model for Deep-Submicron MOSFET's," IEEE Trans. on Electron Devices, Vol.40, No.10 pp.1883-1885, Oct. 1993,
  • M. Fujishima, K. Asada, Y. Omura, and K. Izumi, "Low-power 1/2 Frequency Dividers Using 0.1μm CMOS Circuits Built with Ultrathin SIMOX Substrates," IEEE Journal of Solid-State Circuits, Vol.28, No.4, pp.510-512, Apr. 1993,
  • M. Fujishima, M. Ikeda, K. Asada, Y. Omura, and K. Izumi, "Analytical Modeling of Dynamic Performance of Deep Sub-micron SOI/SIMOX Based on Current-Dwlay Product," IEICE TRANS. ELECTRON.,, Vol.E75-C, No.12, Dec. 1992,
  • M. Fujishima, M. Ikeda, K. Asada, Y. Omura, and Y. Izumi, "Analytical Modeling of Dynamic Performance of Deep Submicron SOI/SIMOX Based on Current-Delay Product," IEICE Trans. on Electronics, Vol. E75-C, No.12, Dec. 1992,
  • 張 洪明 and 浅田 邦博, "Layout Design with Two Dimension MOSFET Cells," 電子情報通信学会論文誌, Vol.J75-A,No.5,pp.960-962, 1992,
  • T. Ohmameuda, H. Miki, K. Asada, T. Sugano, and Y. Ohji, "Thermodynamical Calculation and Experimental Confirmation of the Density of Hole Traps in SiO2 Films," Japanese Journal of Applied Physics, Vol.30,No.12A,pp.L1993-L1995, Dec. 1991,
  • Y. Tajima, K. Asada, and T. Sugano, "1/5 Power Law in PN-Junction Failure Mechanism Cased by Electrical-Over-Stress," IEICE Transactions, Vol.E75-C,No.2,pp.207-215, Feb. 1991,
  • H. Miki, T. Ohmameuda, M. Kumon, K. Asada, and T. Sugano, "Subfemtojoule Deep Submicrometer-Gate CMOS Built In Ultra-Thin Si Film on SIMOX Substrates," IEEE Transactions Electron Devices, Vol.38,No.2,pp.373-377, Feb. 1991,
  • M. Fujishima, K. Asada, and T. Sugano, "Evaluation of Delay-Time Degradation of Low-Voltage BiCMOS Based on a Novel Analytical Delay-Time Modeling," IEEE Journal Solid-State Circuits, Vol.26,No.1,pp.25-31, Jan. 1991,
  • 戴 志堅 and 浅田 邦博, (in Japanese) "回路トポロジーの多段分解による面積最小回路の一合成手法," 電子情報通信学会論文誌, J74-A, 1991,
  • 趙 慶録 and 浅田 邦博, (in Japanese) "One-hot Code状態割当と2-AND論理を用いたVLSI向き非同期回路の合成," 電子情報通信学会論文誌, J74-A巻,2号,pp.218-226, 1991,