Ikeda Lab.

Publications

  • Y. Yachide, Y. Oike, M. Ikeda, and K. Asada, "Real-Time 3-D Measurement System Based on Light-Section Method Using Smart Image Sensor," in Proc. of IEEE International Conference on Image Processing(ICIP), pp. 1008 -- 1011,Sep. 2005,
  • N. Li, M. Ikeda, and K. Asada, "Analysis of Low Noise ThreePhase Asynchronous Data Transmission," in Proc. of European Solid-State Circuits Conference (ESSCIRC), pp. 479 -- 482,Sep. 2005,
  • T. Iizuka, M. Ikeda, and K. Asada, "Computational Cost Reduction for Minimum-Width Transistor Placement of Arbitrary Circuit Structures," in Proc. of IPSJ DA Symposium 2005, pp. 121 -- 126,Aug. 2005,(IPSJ Yamashita SIG Research Award).
  • T. Nakura, M. Ikeda, and K. Asada, "Preliminary Experiments for Power Supply Noise Reduction Using On-Board Stubs," IEICE Trans. on Electronics, Vol.E88-C, No.8, pp.1734-1739, Aug. 2005,
  • T. Iizuka, M. Ikeda, and K. Asada, "Computational Cost Reduction for Minimum-Width Transistor Placement of Arbitrary Circuit Structures," in Proc. of IPSJ DA Symposium 2005, pp. 121 - 126,Aug. 2005,
  • H. Yoshida, M. Ikeda, and K. Asada, "An Algebraic Approach for Synthesizing Circuits with Minimum Number of Transistors," in Proc. of IPSJ DA Symposium 2005, pp. 133 - 138,Aug. 2005,
  • T. Iizuka, M. Ikeda, and K. Asada, "Yield Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization," IEICE Trans. on Fundamentals,Vol. E88-A, No. 7, pp. 1957 -- 1963, Jul. 2005,
  • U. Ekinciel, H. Yamaoka, H. Yoshida, M. Ikeda, and K. Asada, "A Performance Driven Module Generator for a Dual-Rail PLA with Embedded 2-Input Logic Cells," IEICE Trans. on Information and Systems, Vol. E88-D, No. 6, pp. 1159 -- 1167, Jun. 2005,
  • T. Nakura, M. Ikeda, and K. Asada, "Feedforward Active Substrate Noise Cancelling Technique using Power Supply di/dt Detector," JSAP/IEEE Symposium on VLSI Circuits (VLSI Symp.) Dig. of Tech, Papers, pp. 284 -- 287,Jun. 2005,
  • T. Nakura, M. Ikeda, and K. Asada, "On-Chip di/dt Detector Circuit," IEICE Trans. on Electronics,Vol. E88-C, No. 5, pp. 782 -- 787, May. 2005,(IEICE Best Paper Award 2005).
  • T. Nakura, M. Ikeda, and K. Asada, "di/dt Detector Core for Power Supply of LSI," 7th IP Award from LSI IP Design Award CommitteesMay. 2005,(the Outstanding IP Award 2005).
  • T. Iizuka, M. Ikeda, and K. Asada, "Yield-Optimized CMOS Logic Cell Layout IP Synthesis System," 7th IP Award from LSI IP Design Award CommitteesMay. 2005,(Development Promotion).
  • T. Iizuka, M. Ikeda, and K. Asada, "Exact Minimum-Width Transistor Placement Without Dual Constraint for CMOS Cells," in Proc. of ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 74 -- 77,Apr. 2005,
  • Y. Oike, M. Ikeda, and K. Asada, "A 375 x 365 High-Speed 3-D Range-Finding Image Sensor Using Row-Parallel Search Architecture and Multi-Sampling Technique," IEEE Journal of Solid-State Circuits, Vol. 40, No. 2, pp. 444 -- 453, Feb. 2005,
  • T. Nakura, M. Ikeda, and K. Asada, "Stub vs. Capacitor for Power Supply Noise Reduction," IEICE Trans. on Electronics , Vol.E88-C, No.1, pp.125-132, Jan. 2005.
  • T. Nakura, M. Ikeda, and K. Asada, "On-Chip di/dt Detector Circuit," IEICE Trans. on Electronics, Vol. E88-C, No. 5, pp. 782 -- 787, May 2005,
  • T. Yamamoto, M. Ikeda, and K. Asada, "Symbolic Analysis of Performance Fluctuation on Analog Circuits," in Proc. of IEICE Karuizawa Workshop 2005, pp. 31 - 36,May 2005,
  • T. Iizuka, M. Ikeda, and K. Asada, "High-Speed Layout Synthesis for Minimum-Width CMOS Logic Cells via Boolean Satisfiability," IEICE Trans. on Fundamentals, Vol. E87-A, No. 12, pp. 3293 -- 3300, Dec. 2004,
  • Y. Oike, M. Ikeda, and K. Asada, "A Pixel-Level Color Demodulation Image Sensor for Support of Image Recognition," IEICE Trans. on Electronics, Vol. E87-C, No. 12, pp. 1651 -- 1658, Dec. 2004,
  • T. Iizuka, M. Ikeda, and K. Asada, "High Speed Layout Synthesis for Minimum-Width CMOS Logic Cells via Boolean Satisfiability," IEICE Trans. Fundamentals, Vol.E87-A, No.12, pp.3293-3300,Dec. 2004,