- Y. Oike, M. Ikeda, and K. Asada,
"Digital Associative Memories Based on Hamming Distance and Scalable Multi-Chip Architecture,"
in Proc. of IP Based System-on-Chip Design Forum & Exhibition (IP-SOC), pp. 127 -- 130,Dec. 2004,
- T. Iizuka, H. Yoshida, M. Ikeda, K. Asada,
"Hierarchical Layout Synthesis for CMOS Logic Cells via Boolean Satisfiability,"
IEICE Technical Report, vol. 104, no. 478, pp. 1 - 6,Dec. 2004, (in Japanese)
- H. Yoshida, K. De, V. Boppana, M. Ikeda, K. Asada,
"Accurate Pre-Layout Estimation of Intra-cell Parasitics Using Fast Transistor-level Placement,"
IEICE Technical Report, vol. 104, no. 478, pp. 7 - 12,Dec. 2004, (in Japanese)
- Y. Oike, M. Ikeda, and K. Asada,
"Hierarchical Multi-Chip Architecture for High Capacity Scalability of Fully Parallel Hamming-Distance Associative Memories,"
IEICE Trans. on Electronics, Vol. E87-C, No. 11, pp. 1847 -- 1855, Nov. 2004,
- Y. Yachide, Y. Oike, M. Ikeda, K. Asada,
"Implementation of a Real-Time 3-D Imaging System and Application to Multi-Viewpoint Measurement,"
in Proc. of IEICE the 8th Workshop on System LSI in Kitakyushu, pp.255-258,Nov. 2004, (in Japanese)
- Y. Oike, M. Ikeda, and K. Asada,
"A Word-Parallel Digital Associative Engine with Wide Search Range Based on Manhattan Distance,"
in Proc. of IEEE Custom Integrated Circuits Conference (CICC), pp. 295 -- 298,Oct. 2004,
- M. Abbas, M. Ikeda, and K. Asada,
"Noise Effects on Performance of Low Power Design Schemes in Deep Submicron Regime,"
in Proc. of The 19th IEEE International Symposium on Deffet and Fault Tolerance in VLSI Systems (DFT 2004), pp, 87 -- 97,Oct. 2004,
- M. Abbas, M. Ikeda, and K. Asada,
"On High Noise Immunity CMOS Design Scheme with Low Leakage Power Consumption,"
in Proc. of The 17th International Conference on Solid State and Integrated-Circuit Technology (ICSICT 2004), pp, 2031 -- 2034,Oct. 2004,
- Y. Oike, H. Hashimoto, M. Ikeda, K. Asada,
"A Color Demodulation Image Sensor for Support of Image Recognition,"
ITE Technical Report, Vol. 28, No. 59, pp. 9 -- 12,Oct. 2004, (in Japanese)
- U. Ekinciel, M. Ikeda, and K. Asada,
"An SRAM-based Field Programmable Logic Array Design,"
IEICE Society Conference 2004,Sep. 2004,
- T. Nakura, M. Ikeda, K. Asada,
"Power Supply Noise Reduction on LSIs using Off-chip stubs,"
in Proc. of IEICE Society Conference 2004, C-12-1,Sep. 2004, (in Japanese).
- Y. Oike, M. Ikeda, K. Asada,
"Design of Digital Associative Engine for Manhattan Distance Search,"
in Proc. of IEICE Society Conference 2004, C-12-7,Sep. 2004, (in Japanese)
- M. Abbas, M. Ikeda, K. Asada,
"Statistical Evaluation of Logic Errors in Low Power Design Schemes,"
in Proc. of IEICE Society Conference 2004, A-9-3,Sep. 2004, (in Japanese)
- N. Li, M. Ikeda, K. Asada,
"Study of Low EMI Circuit with 3-Phase Transmission Protocol,"
in Proc. of IEICE Society Conference 2004, C-12-5,Sep. 2004, (in Japanese)
- TH. YEN, M. Ikeda, K. Asada,
"Estimatoin of Radiated Electromagnetic Emission from Integrated Circuit Using Short Wire Antenna,"
in Proc. of IEICE Society Conference 2004, B-4-30,Sep. 2004, (in Japanese)
- Y. Oike, M. Ikeda, and K. Asada,
"A High-Speed and Low-Voltage Associative Co-Processor With Exact Hamming/Manhattan-Distance Estimation Using Word-Parallel and Hierarchical Search Architecture,"
IEEE Journal of Solid-State Circuits, Vol. 39, No. 8, pp. 1383 -- 1387, Aug. 2004,
- T. Nakura, M. Ikeda, and K. Asada,
"Design and Measurement of On-chip di/dt Detector Circuit for Power Supply Line,"
in Proc. of IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (AP-ASIC), University Design Forum, pp. 426 -- 427,Aug. 2004,
- T. Nakura, M. Ikeda, and K. Asada,
"Preliminary Experiments for Power Supply Noise Reduction using Stubs,"
in Proc. of IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (AP-ASIC), pp. 286 -- 289,Aug. 2004,
- Y. Oike, M. Ikeda, and K. Asada,
"Design and Implementation of Word-Parallel Digital Associative Memories,"
in Proc. of IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (AP-ASIC), University Design Forum, pp. 428 -- 429,Aug. 2004,
- Y. Oike, M. Ikeda, K. Asada,
"A 1024 x 768 High-Speed and High-Accuracy 3-D Image Sensor,"
in Proc. of ITE Annual Conference 2004, 19-1,Aug. 2004, (in Japanese).