- T. S. Cheung and K. Asada,
"Regenerative Pass-Transistor Logic: A Modular Circuit Technique for High Speed Logic Circuit Design,"
IEICE Trans. on Electronics , Vol.E-79C, No.9, pp.1274-1284, Sep. 1998,
- K. Sekine, S. Nakai, T. Nishimura, K. Shimoi, K. Nishimura, and K. Asada,
"Progress in Electronics, Information and System Engineering,"
Journal of IEE of Japan, Vol.118, No.6, pp.348-354, Jun. 1998,
- K. Asada,
"VDEC (VLSI Design and Education Center): The Center of VLSI Desigh Education in Japan,"
MRS-J NEWS , Vol.10, No.2, pp.4-5, May. 1998,
- K. Asada, J. Akita, and R. Watabe,
"A Tree Structure of Automata for Selective Image Scanning and Its Implementation ,"
Computers & Electrical Engineering, Vol.23, No.6, pp.453-461, Nov. 1997,
- Jeehan Lee, Kunihiro Asada,
"A Synchronous Completion Prediction Adder (SCPA),"
IEICE Trans. Fundamentals, Vol.E80-A, No.3, pp.606-609, Sep. 1997,
- J. Akita and K. Asada,
"An Image Scanning Method with Selective Activation of Tree Structure,,"
IEICE Trans. on Electronics, Vol.E80-C, No.7, pp.956-961, , Jul. 1997,
- M. Song and K. Asada,
"Power Optimization for Data Compressors Based on a Window Detector in a 54 x 54 Bit Multiplier,"
IEICE Trans. on Electronics , Vol.E80-C, No.7, pp.1016-1024, Jul. 1997,
- R. Ikeno, H. Ito, and K. Asada,
"Device Parameter Estimation of SOI MOSFET Using One-Dimensional Numerical Simulation Considering Quantum Mechanical Effects,"
IEICE Trans. on Electronics, Vol.E80-C, No.6, pp.806-811, Jun. 1997,
- M. Aoyagi and K. Asada,
"Initial Stage of Stress-Induced Migration Phenomenon in Aluminum Interconnection on Semiconductort Device,"
Jpn.J.Appl.Physics, Vol.36, Part 1, No.5A, pp.2601-2605, May. 1997,
- T. S. Cheung and K. Asada,
"High-speed high-density adders and multiplier design using Regenerative Pass-transistor Logic,"
IEICE Trans. on Electronics, Vol.E80-C, No.3, pp.478-488, Mar. 1997,
- J. H. Lee and K. Asada,
"A Synchronous Completion Prediction Adder(SCPA),"
IEICE Trans. on Fundamental of Electronics, Communications and Computer Sciences, Vol.E-80A, No.3, pp.606-609, Mar. 1997,
- T. S. Cheung and K. Asada,
"Design of High-speed High-density Parallel adders and multiplier using Regenerative Pass-transistor Logic,"
IEICE Trans. on Electronics, Vol.E-89-C, No.3, pp.478-488, Mar. 1997,
- J. H. Lee and K. Asada,
"A Synchronous Completion Prediction Adder (SCPA),"
IEICE Trans. Fundamentals, Vol.E80-A, No.3, pp.606-609, Mar. 1997,
- K. Hoh, K. Ueda, T. Nanya, H. Yasuura, A. Iwata, N. Ieda, Y. Ishii, and K. Asada,
"VLSI Design Education in Japan,"
Technical Report of the Journal IEICE, Vol.80, No.1, pp.40-62, Jan. 1997,
- K. Hoh and K. Asada,
"Chip fabrication for VLSI design education ,"
Technical Report of 応用物理, Vol.66, No.8, pp.858-861, 1997,
- R. Ikeno and K. Asada,
"Optimum Design of Device Parameters for Switching Energy Minimization using Circuit Simulation,"
電子情報通信学会 論文誌(C-II) , vol.J79-C-II, No.10,pp.525-526, Oct. 1996,
- T. S. Cheung and K. Asada,
"Regenerative Pass-Transistor Logic: A Circuit Technique for High Speed Digital Design,"
IEICE TRANS. ELECTRON.,, Vol.E79-C, No.9, pp.1274-1284, Sep. 1996,
- Makoto Ikeda and K. Asada,
"Partitioned-Bus and Variable-Width-Bus Scheme for Low Power Digital Processors,"
IEICE Transaction on Electronics, Vol.E79-C,No.3, pp.424-429, Mar. 1996,
- Makoto Ikeda and K. Asada,
"Partitioned-Bus and Variable-Width-Bus Scheme for Low Power Digital Processors,"
IEICE Trans. Electron, Vol.E79-C, No.3, pp, Mar. 1996,
- H.Ito and K.Asada,
"Modeling of Leak Current Characteristics in High Frequency Operation of CMOS Circuits Fabricated on SOI Substrate,"
IEICE Trans. on Electronics, Vol.E79-C,No.2, pp.185-191, Feb. 1996,