- Y. Sato, R. Zheng, and K. Asada,
"Design of Pseudo Asynchronous Microprocessor with Completion Detection,"
Technical Report of IEICE., ICD98-17, CPSY98-17, FTS98-17(1998-04) pp.47-52, Apr. 1998,
- K. Asada, T. Nezuka, and J. Akita,
"A Realization of Gray-scale Image Sensor with Quad Tree Scan,"
平成9年度重点領域研究「極限集積化シリコン知能エレクトロニクス」公開シンポジウム, p202-208, Apr. 1998,
- T. Mido, H. Ito, and K. Asada,
"TEST Structure for Characterizing Capacitance Matrix of Multi-layer Interconnections in VLSI,"
Proceeding of International Conference on Microelectronic Test Structures (ICMTS) 110周年記念特集電気電子技術10年の歩み, pp.217-222, Mar. 1998,
- T. Nezuka, J. Akita, and K. Asada,
"A CMOS Image Sensor for Motion Detection with Hierarchical Scan,"
Procedding of the 1998 IEICE General Conference, C-12-49, p.177, Mar. 1998,
- M．Aoyagi and K．Asada ,
"Vacancy distribution in aluminum interconnection on semiconductor device,"
Ext． Abstr． (45th Spring Meet．1998)； Japan Society of Applied Physics and Related Societies，, 29p-N15．(in Japanese), Mar. 1998,
- R. Zheng , M. Ikeda, and K. Asada,
"A Case Study: Design and Implementation of Pseudo-Asynchronous ,"
International Workshop on Logic and Architecture Synthesis '97 , Dec. 1997,
- K. Asada, J. Akita, and R. Watabe,
"A Tree Structure of Automata for Selective Image Scanning and Its Implementation ,"
Computers & Electrical Engineering, Vol.23, No.6, pp.453-461, Nov. 1997,
- Jeehan Lee, Kunihiro Asada,
"A Synchronous Completion Prediction Adder (SCPA),"
IEICE Trans. Fundamentals, Vol.E80-A, No.3, pp.606-609, Sep. 1997,
- Tetsuhisa Mido, Kunihiro Asada
"Delay-Optimum Aspect Ratio of VLSI Interconnections based on New Accurate Capacitance Formulations ,"
European Conference on Circuit Theory and Design , Vol. 2, pp.978-983 Sep. 1997,
- R. Zheng, M. Ikeda, J. H. Lee, and K. Asada,
"Design and Implementation of A Pseudo-Asynchronous Microprocessor,"
1997年電子情報通信学会秋期大会 , C12-22, , Sep. 1997,
- K. Asada, M. Aoyagi, and T. Mido,
"An Analysis on Hi-Frequency Interconnections in VLSI Considering,"
電子情報通信学会 VLSI 設計研究会, 信学技報, VLD97-69, Vol.96, No.269,, Sep. 1997,
- J. H. Lee and K. Asada,
"A synchronous completion prediction adder(SCPA) with high hardware-delayh performance,"
7th International Symposium on IC Technology, Systems & Applications (ISIC-97 ), pp. 60-63, , Sep. 1997,
- K. Nose, R. Ikeno, and K. Asada,
"Simulation Study on Extraction Mechanism of Generated Holes in the Floating-body SOI MOSFETs,"
Technical Report of IEICE,信学技報 Singapore, 9/10-12, Sep. 1997,
- K. Asada, H. Ito, and T. Mido,
"Test Structure for Calculating Capacitance Matrix of Multi Conductors in VLSI,"
1997年電子情報通信学会秋期大会, C-12-5, P.88, Sep. 1997,
- J. Akita and K. Asada,
"A CMOS Image Sensor with Variable Block Access Function for Adaptive Resolution Scan、,"
1997年電子情報通信学会秋季大会, C12-39, Sep. 1997,
- T. Mido and K. Asada,
"Delay-Optimum Aspect Ratio of VLSI Interconnections based on New Accurate Capacitance Formulations,"
European Conference on Circuit Theory and Design '97, Vol.2, pp.978-983, Sep. 1997,
- J. Akita and K. Asada,
"An Image Scanning Method with Selective Activation of Tree Structure,,"
IEICE Trans. on Electronics, Vol.E80-C, No.7, pp.956-961, , Jul. 1997,
- M. Song and K. Asada,
"Power Optimization for Data Compressors Based on a Window Detector in a 54 x 54 Bit Multiplier,"
IEICE Trans. on Electronics , Vol.E80-C, No.7, pp.1016-1024, Jul. 1997,
- T. S. Cheung and K. Asada,
"Design Automation Algorithms for Regenerative Pass-transistor Logic,"
ISCAS (International Symposium on Circuits and Systems), Vol.3 (Cad VLSI) pp.1540-1543, Jun. 1997,
- J. Akita and K. Asada,
"An Image Sensor using Quad Tree for Selective Scanning with Adaptive Resolution,"
1997 IEEE CCD&AIS Workshop, Jun. 1997,