- R. Ikeno, H. Ito, and K. Asada,
"Device Parameter Estimation of SOI MOSFET Using One-Dimensional Numerical Simulation Considering Quantum Mechanical Effects,"
IEICE Trans. on Electronics, Vol.E80-C, No.6, pp.806-811, Jun. 1997,
- T. Mido and K. Asada,
"An Analysis of Current Distribution in Finit Width Interconnection in Hi-Frequency Intergrated System,"
回路実装学会 実装CAE研究会、研究報告, CAE97-1, Jun. 1997,
- M. Aoyagi and K. Asada,
"Initial Stage of Stress-Induced Migration Phenomenon in Aluminum Interconnection on Semiconductort Device,"
Jpn.J.Appl.Physics, Vol.36, Part 1, No.5A, pp.2601-2605, May. 1997,
- M. Ikeda, Y. Tajima, and K. Asada,
"Partitioned and Pipelined Bus Architecuture in VLSI,"
Techniclal Report of IEICE 信学技報, ICD97-4, CPSY97-4, FTS97-4, pp.25-32, Apr. 1997,
- T. S. Cheung and K. Asada,
"High-speed high-density adders and multiplier design using Regenerative Pass-transistor Logic,"
IEICE Trans. on Electronics, Vol.E80-C, No.3, pp.478-488, Mar. 1997,
- T. Mido, M. Ikeda, and K. Asada,
"Bus Data Coding with Low Coupled Signal for Low Power VLSI,"
電子情報通信学会 VLSI設計研究会, VLD96ー108、PP.91-96, Mar. 1997,
- K. Asada and J. Akita,
"Image Sensor using Tree Structure ,"
重点領域研究「知能の極限集積化」特別公開シンポジウム(Symposium on Scientific Research on Priority Arears, "Ultimate Integration of Intelligence on Silicon Electronic Systems"), Mar. 1997,
- T. Mido and K. Asada,
"An Analysis on Hi-Frequency VLSI Interconnections Considering Skin Effect,"
第44回応用物理学会関経連合講演会, 28pーBー4, Mar. 1997,
- M. Ikeda and K. Asada,
"Bus Data Coding for Low Power Chip Interface,"
1997年電子情報通信学会総合大会, C-12-47, Mar. 1997,
- J. Akita and K. Asada,
"Image Data Compression Efficiency using Tree Scanning and Run-length Coding,"
電子情報通信学会春季全国大会, A-6-10, Mar. 1997,
- H. Ito and K. Asada,
"Minimum propagation delay and optimum of LDD Length in 0.1um MOSFET,"
第44回応用物理学会関経連合講演会, 29p-H-14, Mar. 1997,
- S. Komatsu, M. Ikeda, and K. Asada,
"Comparative Study on Bus Architecture and Multiplexer Architecture for Low Power Microprocessor,"
電子情報通信学会春季全国大会, Cー12ー46, Mar. 1997,
- T. Torii and K. Asada,
"A Study of Selector Based Logic Circuit Design,"
電子情報通信学会春季全国大会, A-3-15, Mar. 1997,
- R. Zheng and K. Asada,
"A Case-Study on Architecture and Mapping of EPGA: Implementation of A Microprocessor,"
電子情報通信学会春季全国大会, C-12-7, Mar. 1997,
- Y. Sato and K. Asada,
"A Design of Completion Detection Pipelined Adder,"
電子情報通信学会春季全国大会, Cー12ー39, Mar. 1997,
- J. H. Lee and K. Asada,
"Input Data Dependence in Synchronous Completion Prediction Adder,"
電子情報通信学会春季全国大会, Cー12ー41, Mar. 1997,
- T. Yamashita and K. Asada,
"Signal Recover Circuit with a Latch Sense Amplifier for CPL,"
電子情報通信学会春季全国大会, Cー12ー49, Mar. 1997,
- M. Aoyagi and K. Asada,
"Experimental study of annealing effect on formation in aluminum interconnection,"
The 44th Spring Meeting, Japan Society of Applied Physics and Related Societies, 29a-PC19, Mar. 1997,
- R. Ikeno, H. Ito, and K. Asada,
"SOI Device Parameter Estimation with 2-dimensionally Quantized Mobility Modeling in Electron Inversion Layer,"
第44回応用物理学会関経連合講演会, Mar. 1997,
- J. H. Lee and K. Asada,
"A Synchronous Completion Prediction Adder(SCPA),"
IEICE Trans. on Fundamental of Electronics, Communications and Computer Sciences, Vol.E-80A, No.3, pp.606-609, Mar. 1997,