- R. Ikeno and K. Asada,
"Device Dependent Convergence-ability of Matrix Solution in Device Simulation,"
第57回応用物理学会学術講演会, 7a-V-4, Sep. 1996,
- T. Mido and K. Asada,
"Formulation for Three Dimensional Capacitances of Contiguous Interconnections in VLSI,"
1996年電子情報通信学会秋期大会, C-470、p.131, Sep. 1996,
- K. Asada and T. Mido,
"Optimum Aspect Ratio of Cross Section of VLSI Interconnections Considering RC-Delay,"
1996年電子情報通信学会秋期大会, C-471,p,132, Sep. 1996,
- T. Torii and K. Asada,
"A Study of Input Selected Logic Circuit Design Based on Human Procedure,"
電子情報通信学会ソサイエティ大会, A-53, Sep. 1996,
- T. Yamashita and K. Asada,
"An Application of a Latch Sense Amplifier for CPL,"
電子情報通信学会ソサイエティ大会, C-476, Sep. 1996,
- J. Akita and K. Asada,
"An Implementation of Image Scanning Method with Selective Activation of Tree Structure,"
1996年電子情報通信学会秋期大会, A-54, Sep. 1996,
- K. Asada and J. Akita,
"A Selective Image Scanning Method using Tree Structure of Automata and Its Applications,"
1996年電子情報通信学会秋期大会, ES-3-7, Sep. 1996,
- M. Aoyagi and K. Asada,
"Effect of residual stress on stress-migration lifetime in Aluminum interconnection,"
The 57th Fall Meeting, Japan Society of Applied Physics and Related Societies, 8p-N16, Sep. 1996,
- R. Ikeno and K. Asada,
"Robust simulation for the hysteresis phenomena of SOI MOSFET's by Quasi-Transient Method,"
1996 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'96), P-13, Sep. 1996,
- M. Ikeda, J. H. Lee, T. Zhang, and K.Asada,
"Power Reduction and Performance Improvement in VLSIs,"
1996 IEICE Biwako Workshop, pp.41-45, Sep. 1996,
- 渡部 亮太, 秋田 純一, and 浅田 邦博,
"An Implementation on CMOS Circuit of Tree Structure of Automata for Image Scanning,"
1996年テレビジョン学会年次大会, 3ー6, Jul. 1996,
- 秋田 純一, 渡部 亮太, and 浅田 邦博,
"A Novel Tree Structure of Automata for Selective Scanning of Image Signals,"
1996年テレビジョン学会年次大会, 1996/03/07, Jul. 1996,
- Makoto Ikeda and K. Asada,
"Partitioned-Bus and Variable-Width-Bus Scheme for Low Power Digital Processors,"
IEICE Transaction on Electronics, Vol.E79-C,No.3, pp.424-429, Mar. 1996,
- Makoto Ikeda and K. Asada,
"Partitioned-Bus and Variable-Width-Bus Scheme for Low Power Digital Processors,"
IEICE Trans. Electron, Vol.E79-C, No.3, pp, Mar. 1996,
- 池野 理門, 伊藤 浩, 名倉 徹, and 浅田 邦博,
"Evaluation of SOI MOSFET Threshold Voltage using 1-D Device Simulation,"
電子情報通信学会 シリコン材料・デバイス研究会、SDM94-208、, Mar. 1996,
- 浅田 邦博 and 秋田 純一,
"Intelligent Low Power Device and Circuit,"
重点領域研究「知能の極限集積化」特別公開シンポジウム, Mar. 1996,
- 池田 誠 and 浅田 邦博,
"Power Reduction using Variable-Width Scheme in Adder,"
96 電子情報通信学会総合大会, pp.C-555, Mar. 1996,
- 秋田 純一 and 浅田 邦博,
"Image Scanning Method with Data Compression Using Tree Structure of Automata,"
電子情報通信学会春季全国大会, Mar. 1996,
- 三堂 哲寿 and 浅田 邦博,
"Simulation of VLSI Interconnections Considering Inductive Coupling Crosstalk Noise,"
第43回応用物理学会関係連合講演会シンポジウム講演, Mar. 1996,
- 張 子誠 and 浅田 邦博,
"A 3.3ns 8x8 bit Parallel Multiplier Using Regenerative Pass-transistor Logic,"
電子情報通信学会 1996年全国春季大会, Mar. 1996,