- T. S. Cheung and K. Asada,
"Design of High-speed High-density Parallel adders and multiplier using Regenerative Pass-transistor Logic,"
IEICE Trans. on Electronics, Vol.E-89-C, No.3, pp.478-488, Mar. 1997,
- J. H. Lee and K. Asada,
"A Synchronous Completion Prediction Adder (SCPA),"
IEICE Trans. Fundamentals, Vol.E80-A, No.3, pp.606-609, Mar. 1997,
- K. Hoh, K. Ueda, T. Nanya, H. Yasuura, A. Iwata, N. Ieda, Y. Ishii, and K. Asada,
"VLSI Design Education in Japan,"
Technical Report of the Journal IEICE, Vol.80, No.1, pp.40-62, Jan. 1997,
- T. Mido and K. Asada,
"Crosstalk Noise in High Density and High Speed Interconnections due to Inductive Coupling,"
Proceeding of ASP-DAC'97, pp.215-220, Jan. 1997,
- K. Asada and K. Hoh,
"VLSI Design and Education Center (VDEC) Current status and future plan,"
Proceed. of the Asia and South Pacific Design Automation Conference 1997 (ASP-DAC '97), pp.365-369,Jan.28-31,1997, Makuhari Messe, Jan. 1997,
- K. Asada and K. Hoh,
"VLSI Design and Education Center (VDEC) Current status and future plan,"
Proceeding of ASP-DAC'97, pp.365-369,Jan.28-31,1997, Makuhari Messe, Jan. 1997,
- K. Hoh and K. Asada,
"Chip fabrication for VLSI design education ,"
Technical Report of 応用物理, Vol.66, No.8, pp.858-861, 1997,
- M. Ikeda and K. Asada,
"Bus Data Coding with Zero Suppression for Low Power Chip Interface,"
IFIP International Workshop on Logic and Architecture Synthesis, pp.267-274, Dec. 1996,
- T. Mido and K. Asada,
"Delay Model for Microstrip Lines Considering Skin Effect for Over 1GHz Operation,"
回路実装学会 第8回ワークショップ, Nov. 1996,
- M. Ikeda, J. H. Lee, R. Zheng, and K. Asada,
"Power Reduction and Performance Improvement in VLSIs,"
電子情報通信学会 LSI設計技術の未来を考える琵琶湖ワークショップ ポスター発表, pp.41-45, Nov. 1996,
- M. Aoyagi and K. Asada,
"Initial stage of stress-migration phenomenon in aluminum interconnection on semiconductor device,"
Technical Report of IEICE, SDM96-132,, Vol.96, No.360, pp.1-7 , Nov. 1996,
- T. Mido and K. Asada,
"Delay Model for Mictostrip Lines Considering Skin Effect for Over 1GHz Operation,"
JIPC 8th Workshop, Nov. 1996,
- K. Asada and J. Akita,
"A Tree Structure of Automata for Selective Image Scanning and Its Implementation ,"
4th Int'l Conf.of Soft Computing (IIzuka'96 ) , A-4-1, Oct. 1996,
- R. Ikeno and K. Asada,
"Optimum Design of Device Parameters for Switching Energy Minimization using Circuit Simulation,"
電子情報通信学会 論文誌(C-II) , vol.J79-C-II, No.10,pp.525-526, Oct. 1996,
- T. Mido and K. Asada,
"Accurate Capacitance Formulas for VLSI Interconnections Based on Finite Element Analysis,"
Proceedings of ANSYS'96 Conference in Japan, pp.239-245, Oct. 1996,
- T. S. Cheung and K. Asada,
"Regenerative Pass-Transistor Logic: A Circuit Technique for High Speed Digital Design,"
IEICE TRANS. ELECTRON.,, Vol.E79-C, No.9, pp.1274-1284, Sep. 1996,
- T. Mido and K. Asada,
"New Capacitance Formulation and Delay Optimum Aspect Ratio for VLSI Interconnections,"
電子情報通信学会 VLSI設計研究会、通信学会技術報告, VLD96-49,Vol.96, No.259, pp.55-60, Sep. 1996,
- S. Komatsu, R. Ikeno, H. Ito, and K. Asada,
"Design parameter dependence and optimization of drain characteristics of DTMOS,"
電子情報通信学会 VLSI設計研究会、通信学会技術報告, VLD96ー43,Vol.96,No.259, Sep. 1996,
- M. Ikeda and K. Asada,
"Signal Transition Oriented Placement and Routing for Power Reduction,"
電子情報通信学会ソサイエティ大会, SA-2-4, Sep. 1996,
- J. H. Lee and K. Asada,
(in Japanese) "同期式完了予測型加算機,"
電子情報通信学会ソサイエティ大会, C-504, Sep. 1996,