- Y. Oike, M. Ikeda, and K. Asada,
"High Performance Photo Detector for Modulated Lighting,"
in Proc. of IEEE International Conference on Sensors (IEEE SENSORS), pp.1456 - 1461, Jun. 2002,
- Y. Oike, M. Ikeda, and K. Asada,
"High-sensitivity and Wide-dynamic-range Range Finder and Its Applications,"
in Proc. of the 5th Biannual World Automation Congress (WAC 2002), pp.417 - 422, Jun. 2002,
- Y. Oike, M. Ikeda, and K. Asada,
"Smart Sensor Architecture for Real-Time High-Resolution 3-D Measurement and Its Implementation,"
ITE Technical Report, vol. 26, no. 41, pp.37-40, Jun. 2002,
- Y. Oike, M. Ikeda, and K. Asada,
"High Perfomance Photo Detector for Modulated Lighting,"
in Proc. of IEEE International Conference on Sensors (IEEE SENSORS), pp.1456-1461, Jun. 2002,
- K. Asada,
"VLSI Design Activities in Japanese Academia and Future Prospects toward SoC Design in Deep-sub micron technologies,"
The 2nd Taiwan-Japan Microelectronics International Symoposium, pp.235-242, Apr. 2002,
- Y. Oike, M. Ikeda, and K. Asada,
"High-Speed Content-Addressable Memory Using Synchronous Hamming Distance Search Circuits,"
IEICE Technical Report, vol. 102, no. 2, pp.19-24, Apr. 2002,
- K. Asada,
"VLSI Design Activities in Japanese Academia and Future Prospects toward SoC Design in Deep-sub micron technologies,"
The 2nd Taiwan-Papan Microelectronics International Symoposium, pp.235-242 (National Chiao Tung University, Hsinchu, Taiwan 新竹 国立交通大学）, Apr. 2002,
- K. Asada,
"Fundamentals and Advanced Features for VLSI Design Activities Supported by Kunihiro Asada, VDEC, Japan,"
1CFES 2002 (The International Conference on Fundamentals of Electronics, Communications and Computer Sciences) Mar.27-28, 2002, Waseda Univ.,
- K. Asada,
"AFuture opening Semiconductor Technology - Number of VLSI design researchers in Universities becomes 4 times in 6 years, IP reuse enbiromentation,"
Nikkei Micro Device, Special Ed., pp.7, Mar. 2002,
- K. Asada, T. Nezuka, and Y. Oike,
"Real-Time 3-D Measurement System Using Smart Access Image Sensor,"
in Proc. of Scientific Research on Priority Areas Symposium, pp.3-12, Mar. 2002,
- Y. Oike, M. Ikeda, and K. Asada,
"New Pixel Architecture for High-Sensitivity Position Detection,"
in Proc. of IEICE General Conference 2002, C-12-47 集積回路C(アナログ) pp.129, Mar. 2002,
- K. Asada,
"Fundamentals and Advanced Features for VLSI Design Activities Supported by Kunihiro Asada, VDEC, Japan,"
ICFES 2002 (The International Conference on Fundamentals of Electronics, Communications and Computer Sciences) Mar.27-28, 2002, Waseda Univ., SS-4 Roles ofChip Fabrication Service for VLSI Design Educaation, Mar. 2002,
- H. Yoshida, H. Yamaoka, M. Ikeda, and K. Asada,
"Logic Synthesis for AND-XOR-OR type Sense-Amplifying PLA,"
Proceedings of the 7th Asia and South Pacific Design Automation Conference and 15th International Conference on VLSI Design (India) IEEE Int. Conf. on VLSI Design & ASP-DAC, pp. 166-171, Jan. 2002,
- T. Ishihara and K. Asada,
"An Architectural Level Energy Reduction Technique for Deep-Submicron Cache Memories,"
ASP-DAC 2002 (India), pp.274-287, Jan. 2002,
- Y. Oike, M. Ikeda, and K. Asada,
"High-sensitivity and Wide-dynamic-range Position Sensor Using Logarithmic-response and Correlation Circuit,"
IEEE Int. Conf. on VLSI Design & ASP-DAC (the Best Design Award)", Jan. 2002,
- H. Yoshida, H. Yamaoka, M. Ikeda, and K. Asada,
"Logic Synthesis for PLA with 2-input Logic Elements,"
in Proc. of IEEE Int. Symp. on Circuits and System, pp.373-376, May 2002,
- T. Ishihara, S. Komatsu,M. Miyama,M. Yoshimoto, M. Hirata, M. Fujita and K. Asada,
"An Inter-University Joint Program for a Trial of IP-Based System LSI Design,"
Proc. of the 4th European Workshop on Microelectronics Education, pp.129-132, May 2002,,
- K. Asada,
"Current status of VDEC IP project and future plan,"
電子情報通信学会技術研究報告 VLSI設計技術, VLSI2001-85-88, pp.1-13, Nov. 2001,
- H. Yoshida, H. Yamaoka, M. Ikeda, and K. Asada,
"Logic Synthesis for PLA with 2-input Logic Elements,"
電子情報通信学会技術報告, CPSY2001-72, Nov. 2001,
- T. Ishihara and K. Asada,
"A Leak Energy Reduction Techineque for Deep Submicron Cache Memories,"
信学技報 IEICE Technical Report, CPSY2001-61，pp.1-6, Nov. 2001,