Ikeda Lab.

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論文誌等での発表

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  • Nguyen Ngoc Mai-Khanh, Masahiro SASAKI, and Kuhiniro ASADA, "A Millimeter-Wave Resistor-less Pulse Generator with a New Dipole-Patch Antenna in 65-nm CMOS," Springer Analog Integrated Circuits and Signal Processing, Vol.73 Issue 3 pp.789-799 Jul. 2012.
  • B. Devlin, M. Ikeda, K. Asada, "Energy Minimum Operation with Self Synchronous Gate-Level Autonomous Power Gating and Voltage Scaling," IEICE Trans. on Electronics, Vol. E95-C, No.4, pp. 546-554,Apr. 2012.
  • T. Iizuka, S. Miura, R. Yamamoto, Y. Chiba, S. Kubo, K. Asada "580fs-Resolution Time-to-Digital Converter utilizing Differential Pulse-Shrinking Buffer Ring in 0.18um CMOS Technology," IEICE Trans. on Electronics, Vol. E95-C, No.4, pp. 661-667,Apr. 2012.
  • T. Iizuka, K. Asada "All-Digital PMOS and NMOS Process Variability Monitor Utilizing Shared Buffer Ring and Ring Oscillator," IEICE Trans. on Electronics, Vol. E95-C, No.4, pp. 627-634,Apr. 2012.
  • J. Kim, T. Nakura, H. Takata, K. Ishibashi, M. Ikeda, K. Asada, "On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction," IEICE Trans. on Electronics, Vol. E95-C, No.4, pp. 643-650,Apr. 2012.
  • H. Yabe, M. Ikeda "3-D Range Map Acquisition System Based on CMOS Image Sensor Using Time-Multiplexing Structured Pattern," IEICE Trans. on Electronics, Vol. E95-C, No.4, pp. 635-642,Apr. 2012.
  • T. Nakura, K. Asada, "Low Pass Filter-less Pulse Width Controlled PLL Using Time to Soft Thermometer Code Converter," IEICE Trans. on Electronics, Vol. E95-C, No.2, pp. 297-302,Mar. 2012.
  • N. N. Mai Khanh, M. Sasaki and K. Asada, "A 65-nm CMOS Fully Integrated Shock-Wave Antenna Array with On-chip Jitter and Pulse-Delay Adjustment for Millimeter-Wave Active Imaging Application," IEICE Trans. on Electronics, Vol. E94-A, No.12, pp. 2554-2562,Dec. 2011.
  • T. Iizuka, M. Ikeda, and K. Asada, "Timing-Aware Cell Layout Regularity Enhancement for Reduction of Systematic Gate Critical Dimension Variation," AICIT Journal of Next Generation Information Technology, Vol. 2, No. 4, pp. 1-9,Nov. 2011.(invited)
  • N. N. Mai Khanh, M. Sasaki and K. Asada, "A 0.25-um Si-Ge Fully Integrated Pulse Transmitter with On-chip Loop Antenna Array towards Beam- Formability for Millimeter-Wave Active Imaging," IEICE Trans. on Electronics, Vol. E94-C, No.10, pp. 1626-1633Oct. 2011.
  • B. Devlin, M. Ikeda, and K. Asada "A 65 nm Gate-Level Pipelined Self-Synchronous FPGA for High Performance and Variation Robust Operation ," IEEE Journal of Solid-State Circuits, Vol. 46, No.11, pp. 2500-2513,Oct. 2011.
  • S. Mandai, T. Iizuka, T. Nakura, M. Ikeda, and K. Asada, "1.0ps Resolution Time-to-Digital Converter based on Cascaded Time-Difference-Amplifier utilizing Differential Logic Delay Cells," IEICE Trans. on Electronics, Vol. E94-C, No.6, pp. 1098-1104,Jun. 2011.
  • S. Mandai, T. Nakura, T. Iizuka, M. Ikeda, and K. Asada, "Cascaded Time Difference Amplifier With Differential Logic Delay Cell," IEICE Trans. on Electronics, Vol. E94-C, No.4, pp. 654-662,Apr. 2011.
  • J. Kim, T. Nakura, H. Takata, K. Ishibashi, M. Ikeda, and K. Asada, "On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch," IEICE Trans. on Electronics, Vol. E94-C, No.4, pp. 511-519,Apr. 2011.
  • T. Iizuka, J. Jeong, T. Nakura, M. Ikeda, and K. Asada, "All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter," IEICE Trans. on Electronics, Vol. E94-C, No.4, pp. 487-494,Apr. 2011.
  • S. Mandai, T. Momma, M. Ikeda, and K. Asada, "Variable Length Coded Address Compression for High-Speed 3-D Range-Finder Using Light-Section Method," IEICE Trans. On Electronics, Vol. E94-C, No.1, pp. 124-127,Jan. 2011.
  • S. Ergun, U. Guler, and K. Asada, "A High Speed IC Truly Random Number Generator Based on Chaotic Sampling of Regular Waveform," IEICE Trans. On Electronics, Vol. E94-A No.1  pp.180-190,Jan. 2011.
  • T. Iizuka and K. Asada, "All-Digital Ramp Waveform Generator for Two-Step Single-Slope ADC," IEICE Electronics Express, vol. 8, no.1, pp. 20-25 Jan. 2011.
  • S. Mandai, T. Nakura, M. Ikeda, and K. Asada, "A 8bit Two Stage Time-to-Digital Converter using Time Difference Amplifier," IEICE Electronics Express, vol. 7, no.13, pp. 943-948 Jul. 2010.
  • B.S. Delvin, T. Nakura, M. Ikeda, and K. Asada, "A Low Power and High Throughput Self Synchronous FPGA Using 65 nm CMOS with Throughput Optimization by Pipeline Alignment," IEICE Trans. On Electronics,Vol. E93-A, pp. 1319-1328,Jul. 2010.
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