- T. Nakura, S. Mandai, M. Ikeda, and K. Asada,
"Time Difference Amplifier with Robust Gain Using Closed-Loop Control,"
IEICE Trans. on Electronics, Vol. E93-C, No. 3, pp. 303-308, Mar. 2010,
- S. Mandai, T. Nakura , M. Ikeda , K. Asada,
"Dual Imager Core Chip with 24.8 rangemap/s 3-D and 58 fps 2-D Simultaneous Capture Capability,"
IEICE Trans. on Electronics, Vol. E92-C, No.6, Jun. 2009,
- Y.Yachide, M. Ikeda, and K. Asada,
"Time-Division-Based Multiple-Viewpoint 3-D Measurement System for Real-Time, High-Speed, and High-Accuracy Model Movie Acquisition,"
Journal of Image Information and Television Engineers, Vol. 62, No.3, pp. 392 -- 397, Mar. 2008,
- M. Sasaki, M. Ikeda and K. Asada,
“A Temperature Sensor With an Inaccuracy of -1/+0.8℃ Using 90-nm 1-V CMOS for Online Thermal Monitoring of VLSI Circuits,”
IEEE Transactions,Vol.21, Issue 2, pp.201-208, 2008,
- T. Iizuka, M. Ikeda, and K. Asada,
"Timing-Aware Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization,"
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, , Vol. 15, no. 6 , pp. 716--720, Jun. 2007,
- T. Kazama, M. Ikeda, and K. Asad,
"LSI Design Flow for Shot Reduction of Character Projection Electron Beam Direct Writing Using Combined Cell Stencil,"
IEICE Trans. on Fundamentals, Vol. E89-A, No. 12, pp. 3546 -- 3550, Dec. 2006,
- T. Iizuka, M. Ikeda, and K. Asada,
"Exact Minimum-Width Transistor Placement for Dual and Non-Dual CMOS Cells,"
IEICE Trans. on Fundamentals,Vol. E88-A, No. 12, pp. 3485 -- 3491, Dec. 2005,
- T. Nakura, M. Ikeda, and K. Asada,
"Autonomous di/dt Noise Control Scheme for Margin Aware Operation,"
IEEE European Solid-State Circuit Conference (ESSCIRC), sess.8.G.2, pp.467-470, Sep. 2005,
- T. Nakura, M. Ikeda, and K. Asada,
"Preliminary Experiments for Power Supply Noise Reduction Using On-Board Stubs,"
IEICE Trans. on Electronics, Vol.E88-C, No.8, pp.1734-1739, Aug. 2005,
- T. Iizuka, M. Ikeda, and K. Asada,
"Yield Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization,"
IEICE Trans. on Fundamentals,Vol. E88-A, No. 7, pp. 1957 -- 1963, Jul. 2005,
- U. Ekinciel, H. Yamaoka, H. Yoshida, M. Ikeda, and K. Asada,
"A Performance Driven Module Generator for a Dual-Rail PLA with Embedded 2-Input Logic Cells,"
IEICE Trans. on Information and Systems, Vol. E88-D, No. 6, pp. 1159 -- 1167, Jun. 2005,
- T. Nakura, M. Ikeda, and K. Asada,
"On-Chip di/dt Detector Circuit,"
IEICE Trans. on Electronics,Vol. E88-C, No. 5, pp. 782 -- 787, May. 2005,(IEICE Best Paper Award
2005).
- Y. Oike, M. Ikeda, and K. Asada,
"A 375 x 365 High-Speed 3-D Range-Finding Image Sensor Using Row-Parallel Search Architecture and Multi-Sampling Technique,"
IEEE Journal of Solid-State Circuits, Vol. 40, No. 2, pp. 444 -- 453, Feb. 2005,
- T. Nakura, M. Ikeda, and K. Asada,
"Stub vs. Capacitor for Power Supply Noise Reduction,"
IEICE Trans. on Electronics , Vol.E88-C, No.1, pp.125-132, Jan. 2005.
- T. Nakura, M. Ikeda, and K. Asada,
"On-Chip di/dt Detector Circuit,"
IEICE Trans. on Electronics, Vol. E88-C, No. 5, pp. 782 -- 787, May 2005,
- T. Iizuka, M. Ikeda, and K. Asada,
"High-Speed Layout Synthesis for Minimum-Width CMOS Logic Cells via Boolean Satisfiability,"
IEICE Trans. on Fundamentals, Vol. E87-A, No. 12, pp. 3293 -- 3300, Dec. 2004,
- Y. Oike, M. Ikeda, and K. Asada,
"A Pixel-Level Color Demodulation Image Sensor for Support of Image Recognition,"
IEICE Trans. on Electronics, Vol. E87-C, No. 12, pp. 1651 -- 1658, Dec. 2004,
- Y. Oike, M. Ikeda, and K. Asada,
"Hierarchical Multi-Chip Architecture for High Capacity Scalability of Fully Parallel Hamming-Distance Associative Memories,"
IEICE Trans. on Electronics, Vol. E87-C, No. 11, pp. 1847 -- 1855, Nov. 2004,
- Y. Oike, M. Ikeda, and K. Asada,
"A High-Speed and Low-Voltage Associative Co-Processor With Exact Hamming/Manhattan-Distance Estimation Using Word-Parallel and Hierarchical Search Architecture,"
IEEE Journal of Solid-State Circuits, Vol. 39, No. 8, pp. 1383 -- 1387, Aug. 2004,
- K. Asada, and Y. Oike,
"Real-Time and High-Resolution 3-D Imaging System Based on Light-Section Method,"
Image Lab, Japan Industrial Publishing Co., Vol. 15, No. 7, pp. 40 -- 44, Jul. 2004,