Ikeda Lab.

Publications

  • K. Asada, and Y. Oike, "Real-Time and High-Resolution 3-D Imaging System Based on Light-Section Method," Image Lab, Japan Industrial Publishing Co., Vol. 15, No. 7, pp. 40 -- 44, Jul. 2004,
  • T. Iizuka, M. Ikeda, and K. Asada, "Minimum-Width Transistor Placement Method via Boolean Constraints for Non-Complementary Transistors," in Proc. of IPSJ DA Symposium 2004, pp. 121 - 126,Jul. 2004, (in Japanese).
  • H. Yamaoka, M. Ikeda, and K. Asada, "A High-Speed and Area-Efficient Dual-Rail PLA Using Divided and Interdigitated Column Circuits," IEICE Trans. on Electronics,Vol. E87-C, No. 6, pp. 1069 -- 1077, Jun. 2004,
  • Y. Oike, M. Ikeda, and K. Asada, "Smart Image Sensor with High-Speed and High-Sensitivity ID Beacon Detection for Augmented Reality System," Journal of Image Information and Television Engineers, Vol. 58, No. 6, pp. 835 -- 841, Jun. 2004,
  • Y. Oike, M. Ikeda, and K. Asada, "Smart Access Image Sensors for High-Speed and High-Resolution 3-D Measurement Based on Light-Section Method," Int. Journal of Intelligent Automation and Soft Computing (AutoSoft), AutoSoft Press, Vol. 10, No. 2, pp. 105 -- 128, Jun. 2004,
  • Y. Oike, M. Ikeda, and K. Asada, "A Pixel-Level Color Image Sensor With Efficient Ambient Light Suppression Using Modulated RGB Flashlight and Application to TOF Range Finding," IEEE Symposium on VLSI Circuits (VLSI Symp.) Dig. of Tech., Papers, pp. 298 -- 301,Jun. 2004,
  • T. Nakura, M. Ikeda, and K. Asada, "Power Supply di/dt Measurement using On-chip di/dt Detector Circuit," IEEE Symposium on VLSI Circuits (VLSI Symp.) Dig. of Tech., Papers, pp. 106 -- 109,Jun. 2004,
  • Y. Oike, M. Ikeda, and K. Asada, "A High-Speed XGA 3-D Image Sensor and Its Applications," in Proc. of the 6th Biannual World Automation Congress (WAC 2004),Jun. 2004,
  • Y. Oike, M. Ikeda, and K. Asada, "A High-Speed 3-D Range Finder Using Row-Parallel Search Architecture," IEICE Technical Report, vol. 104, no. 174, pp. 7 - 10,Jun. 2004, (in Japanese).
  • Y. Oike, M. ikeda, and K. Asada, "A High-Speed Associative Processor Using Hierarchical Search Architecture Based on Hamming Distance," 6th IP Award from LSI IP Design Award CommitteesJun. 2004,(the Outstanding IP Award 2004).
  • Y. Oike, M. Ikeda, and K. Asada, "Design and Implementation of Real-Time 3-D Image Sensor With 640 x 480 Pixel Resolution," IEEE Journal of Solid-State Circuits, Vol. 39, No. 4, pp. 622 -- 628, Apr. 2004,
  • T. Nakura, M. Ikeda, and K. Asada, "On-chip di/dt Detector Circuit for Power Supply Line," in Proc. of IEEE International Conference on Microelectronic Test Structure (ICMTS), pp.19-22,Mar. 2004,
  • T. Iizuka, M. Ikeda, and K. Asada, "Exact Wiring Fault Minimization via Comprehensive Layout Synthesis for CMOS Logic Cells," in Proc. of IEEE International Symposium on Quality Electronic Design (ISQED), pp. 377 - 380,Mar. 2004,
  • K. Asada, Y. Oike, and M. Ikeda, "Three Dimensional Image Sensor for Real Time Application Based on Triangulation," in Proc. of International Symposium on Electronics for Future Generations, pp. 95 - 100,Mar. 2004,
  • T. Nakura, M. Ikeda, and K. Asada, "Recent Trend of Circuit Designs," JIEP Technical Report, pp.131-132,Mar. 2004,
  • Y. Oike, M. Ikeda, and K. Asada, "A High-Speed and Low-Voltage Associative Co-Processor Using Word-Parallel and Hierarchical Search Architecture," in Proc. of IEICE General Conferece 2004, C-12-34, pp. 138,Mar. 2004,
  • H. Ikehata, M. Song, M. Ikeda, and K. Asada, "Comparison between DCVSL Domino and Static CMOS by High Speed MULTIPLIER," in Proc. of IEICE General Conferece 2004, A-1-13, pp. 13,Mar. 2004,
  • T. Ogawa, M. Ikeda, and K. Asada, "Analysis on Contactless Data Transfer Systems between System LSIs," in Proc. of IEICE General Conferece 2004, A-1-22, pp. 22,Mar. 2004,
  • Y. Yachide, Y. Oike, M. Ikeda, and K. Asada, "3D Measurement Method in an Arbitrary Viewpoint Based on Light-Section Method by Using Smart Image Sensor," ITE Technical Report, Vol. 28, No. 20, pp. 33 - 36,Mar. 2004,
  • H. Yamaoka, H. Yoshida, M. Ikeda, and K. Asada, "A Logic-Cell-Embedded PLA (LCPLA): An Area-Efficient Dual-Rail Array Logic Architecture," IEICE Trans. Electron., vol. E87-C, no. 2, pp. 238-245, Feb. 2004,