- 張 子誠 and 浅田 邦博,
"High Speed CMOS Logic Circuit Design using Sub-Vdd Interfacing Technique,"
1994年電子情報通信学会 秋季大会, SC-9-5, pp.243-4, Sep. 1994,
- 張 子誠, 李 知漢, and 浅田 邦博,
"A 100MHz Serial Data Synchronizer Using Clock Separated Logic Blocks,"
1994年電子情報通信学会 秋季全国大会 , C-483 pp.161, Sep. 1994,
- 伊藤 浩, 池田 誠, and 浅田 邦博,
"Measurement of Fringing Capacitance with Ring Oscillator in MOS/SOI Device,"
第55回応用物理学会学術講演会, 19p-ZG-5, Sep. 1994,
- H. Hayashi and J. Akita,
"A Method of Optimal State Code Assignment for Reducing Power Consumption in Synchronous Circuits,"
1994年電子情報通信学会 秋季全国大会, A-67, pp.67, Sep. 1994,
- J. Akita, H. Hayashi, and K. Asada,
"An Estimation and Reduction of Power Consumption in Clock Line of Synchronous Flip-Flops,"
1994年電子情報通信学会 秋季全国大会, A-68, pp.68, Sep. 1994,
- K. Asada and M. Lee,
"Ultimate Lower Bound of Power for MOS Integrated Circuits and their Applications,"
IEICE Trans. on Electronics, Vol.E77-C, No.7, pp.1131-1137, Jul. 1994,
- K-R. Cho, K. Okura, and K. Asada,
"Experimental Design of a 32-bit Fully Asynchronous Microprocessor (FAM),"
IEICE Trans. on Electronics, Vol.E77-C, No.4, Apr. 1994,
- M. Lee and K. Asada,
"Ultimate Lower Bound of Power for MOS Integrated Circuits,"
Silicon Materials and Device Research Meeting (SDM), Mar. 1994,
- R. Ikeno and K. Asada,
"High-Speed Method for Device Simulations by Block Division,"
The Japan Society of Applied Physics, Mar. 1994,
- M. Lee and K. Asada,
"Ultimate Lower Bound of power for MOSFET Integrated Circuits,"
Silicon Materials and Device Research Meeting (SDM), Mar. 1994,
- M. Lee and K. Asada,
"A proposal to evaluate switching Energy of Recycled Mechanism of a Device,"
Proceedings of the 1994 IEICE Spring Conference, SC-7, Mar. 1994,
- M. LEE and K. Asada,
"A Proposal to Evaluate Minimum Switching Energy of Recycled Mechanism of MOS Device,"
IEICE Spring Conference, SC-7, Mar. 1994,
- 張 子誠, 宋 敏圭, and 浅田 邦博,
"An Architectural Self-Refreshable Analog Memory System,"
1994年電子情報通信学会 春季大会, Mar. 1994,
- M. Ikeda and K. Asada,
"A Reduced-swing Data Transmission Scheme for Resistive Bus Lines in ULSIs,"
The European Design and Test Conference 1994, Proceedings pp. 546-550, Mar. 1994,
- Y. Iwasaki and K. Asada,
"Numerical Analysis of Durable Power MOSFET Using Cylindrical Device Simulator,"
IEICE Trans. Fundamentals, Vol.E77-A, No.2, pp.371-379, Feb. 1994,
- J. Akita and K. Asada,
"A Method for Reducing Power Consumption of CMOS Logic Based on Signal Transition Probability,"
EDAC-ETC Euro Asic 1994, Feb. 1994,
- M. Ikeda and K. Asada,
"A proposal of high speed and low power data transmission method for VLSIs by reduced-swing signal,"
IEICE Transaction on Electronics, E76-A No.10 pp1666-1675, Oct. 1993,
- M. Lee and K. Asada,
"Deep-Submicron CMOS/SIMOX Delay Modeling by Time-Dependent Capacitance Model,"
IEEE Trans. on Electron Devices , Vol.40, No.10, pp.1897-1901, Oct. 1993,
- M. Lee and K. Asada,
"A New proposal for Delay Improvement on CMOS/SOI Future Technology,"
IEICE Trans. on Electronics, Vol.E76-C, No.10, pp.1513-1522, Oct. 1993,
- M. Fujishima and K. Asada,
"A Nonpinchoff Gradual Channel Model for Deep-Submicron MOSFET's,"
IEEE Trans. on Electron Devices, Vol.40, No.10 pp.1883-1885, Oct. 1993,