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"Data Bypassing Register File for Low Power Microprocessor,"
IEICE Transaction on Electronics, Vol.E78-C, No.10, pp.1470-1472, Oct. 1995,
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"Non-Approximate Evaluation of Macroscopic Quantum Tunneling of Charge for the Two-Junction Case at Arbitrary Temperatures and Bias Voltages,"
Jpn.J.Appl.Phys. , Vol.34(1995), PP.l1230-l1233, Part 2, No.9B, Sep. 1995,
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IEICE Trans. on Electronics, Vol.E78-C, No.4, pp.436-440, Apr. 1995,
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IEICE Trans. on Electronics, Vol.E77-C, No.7, pp.1131-1137, Jul. 1994,
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"Experimental Design of a 32-bit Fully Asynchronous Microprocessor (FAM),"
IEICE Trans. on Electronics, Vol.E77-C, No.4, Apr. 1994,
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IEICE Trans. Fundamentals, Vol.E77-A, No.2, pp.371-379, Feb. 1994,
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"A proposal of high speed and low power data transmission method for VLSIs by reduced-swing signal,"
IEICE Transaction on Electronics, E76-A No.10 pp1666-1675, Oct. 1993,
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"Deep-Submicron CMOS/SIMOX Delay Modeling by Time-Dependent Capacitance Model,"
IEEE Trans. on Electron Devices , Vol.40, No.10, pp.1897-1901, Oct. 1993,
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"A New proposal for Delay Improvement on CMOS/SOI Future Technology,"
IEICE Trans. on Electronics, Vol.E76-C, No.10, pp.1513-1522, Oct. 1993,
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IEEE Trans. on Electron Devices, Vol.40, No.10 pp.1883-1885, Oct. 1993,
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IEEE Journal of Solid-State Circuits, Vol.28, No.4, pp.510-512, Apr. 1993,
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IEICE TRANS. ELECTRON.,, Vol.E75-C, No.12, Dec. 1992,
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IEICE Trans. on Electronics, Vol. E75-C, No.12, Dec. 1992,
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"Layout Design with Two Dimension MOSFET Cells,"
電子情報通信学会論文誌, Vol.J75-A,No.5,pp.960-962, 1992,
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Japanese Journal of Applied Physics, Vol.30,No.12A,pp.L1993-L1995, Dec. 1991,
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"1/5 Power Law in PN-Junction Failure Mechanism Cased by Electrical-Over-Stress,"
IEICE Transactions, Vol.E75-C,No.2,pp.207-215, Feb. 1991,
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IEEE Transactions Electron Devices, Vol.38,No.2,pp.373-377, Feb. 1991,
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IEEE Journal Solid-State Circuits, Vol.26,No.1,pp.25-31, Jan. 1991,
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(in Japanese) "回路トポロジーの多段分解による面積最小回路の一合成手法,"
電子情報通信学会論文誌, J74-A, 1991,
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(in Japanese) "One-hot Code状態割当と2-AND論理を用いたVLSI向き非同期回路の合成,"
電子情報通信学会論文誌, J74-A巻,2号,pp.218-226, 1991,